CDP1824C datasheet(3/6 Pages) INTERSIL

3 / 6 page

6-39

Three-State Output

Leakage Current

IOUT

0, 5

± 0.2

±2.0

± 0.2

± 2

µA

0, 10

± 0.2

±2.0

µA

Input Capacitance

CIN

7.5

Output Capacitance

COUT

NOTES:

1. Typical values are for TA = +25

oC and nominal V

DD.

2. Outputs open circuited; Cycle time = 1

µs.

Static Electrical Speciﬁcations At TA = -40oC to +85oC, Except as Noted: (Continued)

PARAMETER

SYMBOL

CONDITIONS

LIMITS

UNITS

(V)

VIN

(V)

VDD

(V)

CDP1824

CDP1824C

MIN

(NOTE 1)

TYP

MAX

MIN

(NOTE 1)

TYP

MAX

Dynamic Electrical Speciﬁcations at TA = -40oC to +85oC, VDD ±5%, Input tR, tF = 10ns, CL = 50pF, RL = 200kΩ; See Figure 1

PARAMETER

SYMBOL

TEST

CONDITIONS

LIMITS

UNITS

CDP1824D, CDP1824E

CDP1824CD, CDP1824CE

VDD (V)

(NOTE 1)

MIN

(NOTE 2)

TYP

MAX

(NOTE 1)

MIN

(NOTE 2)

TYP

MAX

READ OPERATION

Access Time From

Address Change

tAA

400

710

400

710

200

320

Access Time From

Chip Select

tDOA

300

710

300

710

150

320

Output Active From MRD

tAM

300

710

300

710

150

320

NOTES:

1. Time required by a limit device to allow for the indicated function.

2. Time required by a typical device to allow for the indicated function. Typical values are for TA = +25

oC and nominal V

DD.

NOTES:

1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output.

FIGURE 1. READ CYCLE TIMING DIAGRAMS

MRD

DATA OUT

HIGH IMPEDANCE

tAM

tAA

tDOA

(NOTE 1)

CDP1824, CDP1824C

CDP1824C bảng dữ liệu(PDF) 3 Page - Intersil Corporation

CDP1824C bảng dữ liệu(HTML) 3 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6

bảng dữ liệu tải về

Link URL