3-11

Required Memory Access Time

Address to Data

5

5

5T-375

5T-250

5T-225

5T-175

ns

5

10

5T-250

5T-150

-

-

ns

10

10

5T-190

5T-100

-

-

ns

MRD to TPA

5

5

T/2-25

T/2-18

T/2-20

T/2-15

ns

5

10

T/2-20

T/2-15

-

-

ns

10

10

T/2-15

T/2-10

-

-

ns

NOTE:

PARAMETERS

SYMBOL

TEST CONDITIONS

CDP1802A,

CDP1802AC

CDP1802BC

UNITS

MIN

(NOTE 1)

TYP

MIN

(NOTE 1)

TYP

Timing Waveforms

FIGURE 3. BASIC DC TIMING WAVEFORM, ONE INSTRUCTION CYCLE

FETCH (READ)

EXECUTE (WRITE)

00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00

HI BYTE

LOW BYTE

HI BYTE

LOW BYTE

CLOCK

ADDRESS

TPA

TPB

MRD

MWR

DATA

VALID INPUT DATA

VALID OUTPUT DATA

CDP1802A, CDP1802AC, CDP1802BC