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CD4095BMS bảng dữ liệu(PDF) 7 Page - Intersil Corporation

tên linh kiện CD4095BMS
Giải thích chi tiết về linh kiện  CMOS Gated J-K Master-Slave Flip-Flops
PDF  10 Pages
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nhà sản xuất  INTERSIL [Intersil Corporation]
Trang chủ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD4095BMS bảng dữ liệu(HTML) 7 Page - Intersil Corporation

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CD4095BMS, CD4096BMS
Logic Diagram
FIGURE 1. CD4095BMS AND CD4096BMS LOGIC DIAGRAM
TRUTH TABLES
SYNCHRONOUS OPERATION
(S = 0, R = 0)
ASYNCHRONOUS OPERATION
(J AND K = Don’t Care)
INPUTS BEFORE POSITIVE
CLOCK TRANSITION
OUTPUTS AFTER POSITIVE
CLOCK TRANSITION
INPUTS BEFORE POSITIVE
CLOCK TRANSITION
OUTPUTS AFTER POSITIVE
CLOCK TRANSITION
J*
K*
Q
QS
R
Q
Q
0
0
1
1
0
1
0
1
No Change
0
1
Toggles
No Change
1
0
Toggles
0
0
1
1
0
1
0
1
No Change
0
1
0
No Change
1
0
0
* For CD4095BMS
J = J1
• J2 • J3
K = K1
• K2 • K3
For CD4096BMS
J = J1
• J2 • J3
K = K1
• K2 • K3
0 = VSS, 1 = VDD
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VDD
VSS
J1
*
3
J2
*
4
*
5
FOR
*
5
K1
*
11
K2
*
10
*
9
*
9
TG
CL
2
CL
1
TG
CL
2
CL
1
CL
2
CL
1
TG
CL
2
CL
1
TG
CD4095BMS
J3
FOR
CD4096BMS
J3
FOR
CD4095BMS
J3
FOR
CD4096BMS
J3
SET
*
13
Q
6
Q
8
RESET
*
2
CLOCK
*
12
CL
CL
TG
2
1
OUT
IN
TRANSMISSION GATE
INPUT TO OUTPUT IS:
a) A BIDIRECTIONAL LOW
IMPEDANCE WHEN CONTROL INPUT 1
IS “LOW” AND CONTROL INPUT 2 IS “HIGH”
b) AN OPEN CIRCUIT WHEN CONTROL INPUT 1
IS “HIGH” AND CONTROL INPUT 2 IS “LOW”



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