7-451

CD4071BMS, CD4072BMS, CD4075BMS

FIGURE 5. SCHEMATIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)

FIGURE 6. LOGIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)

Typical Performance Characteristics

FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERIS-

TICS

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

n

p

*

8 (5, 13)

p

p

*

2 (4, 12)

*

1 (3, 11)

n

p

n

p

n

p

ALL INPUTS PROTECTED BY

*

CMOS PROTECTION NETWORK

VDD

VSS

n

p

n

9 (6, 10)

n

p

VDD

14

VSS

7

n

n

J

9 (6, 10)

2 (4, 12)

1 (3, 11)

A

B

8 (5, 13)

C

INPUT VOLTAGE (VIN) (V)

0

5

SUPPLY VOLTAGE (VDD) = 15V

10

15

20

510

15

20

10V

5V

LOAD CAPACITANCE (CL) (pF)

0

SUPPLY VOLTAGE (VDD) = 5V

200

10V

15V

150

100

50

20

40

60

80