7-892

CD4046BMS

Design Information

This information is a guide for approximating the values of external components for the CD4046BMS in a Phase-Locked-

Loop system. The selected external components must be within the following ranges:

5k

Ω≤ R1, R2, RS ≤ 1MΩ

C1

≥ 100pF at VDD ≥ 5V

C1

≥ 50pF at VDD ≥ 10V

CHARACTERISTICS

PHASE

COMPARATOR USED

DESIGN INFORMATION

VCO Frequency

1

VCO Without Offset R2 =

∞

VCO With Offset

2

Same as for Number 1

For Number Signal Input

1

VCO will adjust to center frequency, fo

2

VCO will adjust to lowest operating frequency, fmin

Frequency Lock Range, 2fL

1, 2

2fL = full VCO frequency range

1, 2

2fL = fmax - fmin

Frequency Capture Range, 2fC

1

Loop Filter Component Selection

2

fC = fL

Phase Angle Between Signal and

Comparator

range (2fL)

2

Locks On Harmonic of Center

Frequency

1

Yes

2No

Signal Input Noise Rejection

1

High

2

Low

For further information, see

(1) F. Gardner, “Phase-Lock Techniques” John Wiley and Sons, New York 1966

(2) G. S. Moschytz, “Miniaturized RC Filters Using Phase-Locked Loop”, BSTJ, May, 1965

VDD/2

VDD

VCO INPUT VOLTAGE

VDD/2

VDD

VCO INPUT VOLTAGE

OUT

IN R3

C2

√

(1), (2)

2

πfL

2fC

≈ 1

π

OUT

IN R3

C2

R4

For 2 fC, see Ref. (2)