7-827

CD4033BMS

The CD4033BMS has provisions for automatic blanking of

the non-significant zeros in a multi-digit decimal number

which results in an easily readable display consistent with

normal writing practice. For example, the number 0050.0700

in an eight digit display would be displayed as 50.07. Zero

suppression on the integer side is obtained by connecting

the RBI terminal of the CD4033BMS associated with the

most significant digit in the display to a low-level voltage and

connecting the RBO terminal of that stage to the RBI termi-

nal of the CD4033BMS in the next-lower significant position

in the display. This procedure is continued for each succeed-

ing CD4033BMS on the interger side of the display.

On the fraction side of the display the RBI of the

CD4033BMS associated with the least significant bit is con-

nected to a low-level voltage and the RBO of that

CD4033BMS is connected to the RBI terminal of the

CD4033BMS in the next more-significant-bit position. Again,

this procedure is continued for all CD4033BMS’s on the frac-

tion side of the display.

In a purely fractional number the zero immediately preceding

the decimal point can be displayed by connecting the RBI of

that stage to a high level voltage (instead of to the RBO of

the next more-significant-stage). For example: optional zero

→ 0.7346. Likewise, the zero in a number such as 763.0 can

be displayed by connecting the RBI of the CD4033BMS

associated with it to a high-level voltage.

Ripple blanking of non-significant zeros provides an appre-

ciable savings in display power.

The CD4033BMS has a LAMP TEST input which, when con-

nected to a high-level voltage, overrides normal decoder

operation and enables a check to be made on possible dis-

play malfunctions by putting the seven outputs in the high

state.

The CD4033BMS are supplied in these 16 lead outline pack-

ages:

Braze Seal DIP

H4W

Frit Seal DIP

H2R

Ceramic Flatpack

H6W

Logic Diagram

FIGURE 1. CD4033BMS

DQ

CL

Q

R

CL

DQ

CL

Q

R

CL

DQ

CL

Q

R

CL

DQ

CL

Q

R

CL

DQ

CL

Q

R

CL

CL

1

2

INHIBIT

15

*

RESET

3

16

8

VDD

GND

5

COUT

(CLOCK

4

7

6

11

9

13

12

10

a

b

c

d

e

f

g

VDD

VSS

BY CMOS INPUT

PROTECTION NETWORK

a

b

c

d

e

f

g

SEGMENT

DESIGNATIONS

14

RBO