28F008SA datasheet(13/26 Pages) INTEL

13 / 26 page

VE28F008

271305 – 6

Bus

Command

Comments

Operation

Write

Erase

Data e 20H

Setup

Address e Within block to be

erased

Write

Erase

Data e D0H

Address e Within block to be

erased

StandbyRead

Check RYBY

VOH e Ready VOL e Busy

Read Status Register

Check SR7

1 e Ready 0 e Busy

Toggle OE or CE to update

Status Register

Repeat for subsequent bytes

Full status check can be done after each block or after a

sequence of blocks

Write FFH after the last block erase operation to reset the

device to Ready Array Mode

FULL STATUS CHECK PROCEDURE

271305 – 7

Bus

Command

Comments

Operation

Optional

CPU may already have read

Status Register data in WSM

Read

Ready polling above

Standby

Check SR3

1 e VPP Low Detect

Standby

Check SR45

Both 1 e Command Sequence

Error

Standby

Check SR5

1 e Block Erase Error

SR3 MUST be cleared if set during a block erase attempt

before further attempts are allowed by the Write State

Machine

SR5 is only cleared by the Clear Status Register Command

in cases where multiple blocks are erased before full status is

checked

If error is detected clear the Status Register before

attempting retry or other error recovery

Figure 6 Automated Block Erase Flowchart

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