8X930AX datasheet(36/38 Pages) INTEL

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ADVANCE INFORMATION

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER

Table 19. AC Characteristics for 8x930Ax3 and 8x930Ax4 in Compatibility Mode

Symbol

Parameter

8x930Ax3/8x930Ax4

Compatibility Mode (ns)

(EDF# =1) (1)

AVLL

Address Valid to ALE Low

(0.5+M)T

CLK - 13 [min]

LLAX

Address Hold after ALE Low

10 [min]

WLWH

WR# Pulse Width

(1+N)T

CLK - 10 [min]

LLRL

ALE Low to RD# or PSEN# low

10 [min]

LHAX

ALE High to Address Hold

(1+M)T

CLK - 27 [min]

RLDV

RD# or PSEN# Low to Valid Data/Inst. In

(1+N)T

CLK - 30 [max]

RLAZ

RD# or PSEN# Low to Address Float

3 max (2)

RHDZ

Data Float After PSEN# or RD# High

CLK + 10 [max]

RHLH

RD# or PSEN# High to ALE High (data)

CLK + 10 [min]

WHLH

WR# High to ALE High

CLK+10 [min]

AVDV

Address (demux’ed) Valid to Valid Data/Instr. In

(2+M+N)T

CLK - 38 [max]

AVRL

Address Valid to RD# or PSEN# Low

(1+M)T

CLK - 40 [min]

AVWL

Address (mux’ed) Valid to WR# Low

(1+M)T

CLK - 40 [min]

NOTES:

Device configured with default data float timing for fast memory interface.

Typical value is 0 ns.

Table 20. 8

x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings

Sym-

bol

Parameter

Default Data Float

Timing (ns)

Compatibility Mode

(EDF# =1) (1,2,4,5)

Extended Data Float

Timing (ns)

Increased T

RHDZ

1 mode

(EDF#=0) (1,3,4,5)

LLAX

Address Hold after ALE Low

10 [min]

20 [min]

RLRH

RD# or PSEN# Pulse Width

(1+N)T

CLK - 10 [min]

(1+N)T

CLK - 32 [min]

WLWH

WR# Pulse Width

(1+N)T

CLK - 10 [min]

(1+N)T

CLK - 32 [min]

LLRL

ALE Low to RD# or PSEN# low

10 [min]

20 [min]

LHAX

ALE High to Address Hold

(1+M)T

CLK - 27 [min]

(0.5+M)T

CLK + 15 [min]

RLDV

RD# or PSEN# Low to Valid Data/Inst. In

(1+N)T

CLK - 30 [max]

(1+N)T

CLK - 50 [max]

RHDZ

Instruct. Float After PSEN# or RD# High

10 [max]

(0.5)T

CLK - 5 [max]

NOTES:

Worst-case numbers based on silicon data collected to date.

Device configured with default data float timing for fast memory interface.

Device configured with extended data float timing for slow memory interface.

The values listed are for 12 MHz. For 6 MHz, the value of T

CLK will double and will equal 166.6 ns.

M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.

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