82374EB datasheet(64/208 Pages) INTEL

64 / 208 page

82374EB82374SB

3211 DMA MEMORY LOW PAGE REGISTER DMA MEMORY BASE LOW PAGE REGISTER

087hDMA Channel 0

083hDMA Channel 1

081hDMA Channel 2

082hDMA Channel 3

08BhDMA Channel 5

089hDMA Channel 6

08AhDMA Channel 7

Default Value

00h

Attribute

ReadWrite

Size

8 Bits per channel

Each channel has an 8-bit Low Page register associated with it The DMA memory Low Page register contains

the eight second most-significant bits of the 32-bit address It works in conjunction with the DMA controller’s

High Page register and Current Address register to define the complete (32-bit) address for the DMA channel

This 8-bit register is read or written directly by the processor or bus master It may also be re-initialized by an

autoinitialize back to its original value autoinitialize takes place only after a TC or EOP

Each channel has a Base Low Page Address register located at the same port address as the corresponding

Current Low Page register These registers store the original value of their associated Current Low Page

registers During autoinitialize these values are used to restore the Current Low Page registers to their original

values The 8-bit Base Low Page registers are written simultaneously with their corresponding Current Low

Page register by the microprocessor The Base Low Page registers cannot be read by any external agents

During Scatter-Gather these registers store the 8 bits from the third byte of the current memory address

During a Scatter-Gather transfer the DMA will load a reserve buffer into the base memory address register

In Chaining Mode these register store the 8 bits from the third byte of the current memory address The CPU

will program the base register set with a reserve buffer

Bit

Description

DMA LOW PAGE AND BASE LOW PAGE

These bits represent the eight second most-significant

address bits when forming the full 32-bit address for a DMA transfer Upon reset or Master Clear the

value of these bits is 00h

3212 DMAPDMA PAGE REGISTER

080h 84h 85h 86h 88h 8Ch 8Dh 8Eh

Default Value

xxh

Attribute

ReadWrite

Size

8 Bits

These registers have no effect on the DMA operation These registers provide extra storage space in the IO

space for DMA routines

Bit

Description

DMA PAGE

These bit have no effect on the DMA operation These bits only provide storage space in

the IO map

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