80960JD datasheet(28/61 Pages) INTEL

28 / 61 page

80960JD

PRELIMINARY

4.3

Connection Recommendations

For clean on-chip power distribution, VCC and VSS

pins separately feed the device’s functional units.

Power and ground connections must be made to all

80960JD power and ground pins. On the circuit

board, every VCC pin should connect to a power

plane and every VSS pin should connect to a ground

plane. Place liberal decoupling capacitance near the

80960JD, since the processor can cause transient

power surges.

Pay special attention to the Test Reset (TRST) pin. It

is essential that the JTAG Boundary Scan Test

Access Port (TAP) controller initializes to a known

state whether it will be used or not. If the JTAG

Boundary Scan function will be used, connect a

pulldown resistor between the TRST pin and V

S S. If

the JTAG Boundary Scan function will not be used

(even for board-level testing), connect the TRST pin

to V

SS. Also, do not connect the TDI, TDO, and TCK

pins if the TAP Controller will not be used.

Pins identified as NC must not be connected in

the system.

4.4

DC Specifications

Table 13. 80960JD DC Characteristics

Symbol

Parameter

Min

Typ

Max

Units

Notes

VIL

Input Low Voltage

-0.3

0.8

Input High Voltage

2.0

CC + 0.3

VOL

Output Low Voltage

0.45

IOL = 5 mA

VOH

Output High Voltage

2.4

VCC - 0.5

IOH = -1 mA

IOH = -200 µA

OLP

Output Ground Bounce

< 0.8

(1,2)

CIN

Input Capacitance

PGA

PQFP

fCLKIN = fMIN (2)

OUT

I/O or Output Capacitance

PGA

PQFP

fCLKIN = fMIN (2)

CCLK

CLKIN Capacitance

PGA

PQFP

fCLKIN = fMIN (2)

NOTES:

1. Typical is measured with V

CC = 5.0V and temperature = 25 °C.

2. Not tested.

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