28F004SC datasheet(22/42 Pages) INTEL

22 / 42 page

BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY

PRELIMINARY

SR.7 =

Start

Write 20H,

Block Address

Write D0H,

Block Address

Full Status

Check if Desired

Block Erase

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Read Status

Suspend

Block Erase

Suspend Block

Erase Loop

Yes

Command Sequence

Error

SR.3 =

SR.5 =

SR.4,5 =

Block Erase

Error

Bus

Operation

Command

Comments

Standby

Check SR.4,5

Both 1 = Command Sequence Error

Standby

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status

before full status is checked.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

Check SR.5

1 = Block Erase Error

Standby

Bus

Operation

Command

Comments

Write

Erase Setup

Read

Data = 20H

Addr = Within Block to Be Erased

Check SR.7

1 = WSM Ready

0 = WSM Busy

Repeat for subsequent block erasures.

Full status check can be done after each block erase, or after a

sequence of block erasures.

Write FFH after the last operation to place device in read array mode.

Status Register Data

Standby

Erase

Confirm

Data = D0H

Addr = Within Block to Be Erased

Block Erase

Successful

Standby

Check SR.1

1 = Device Protect Detect

RP# = V

, Block Lock-Bit Is Set

Only required for systems

implementing lock-bit configuration

Device Protect Error

SR.1 =

Check SR.3

1 = V

Error Detect

Range Error

Figure 7. Automated Block Erase Flowchart

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