IDT7132LA55CI datasheet(12/16 Pages) IDT

tên linh kiện	IDT7132LA55CI

Giải thích chi tiết về linh kiện	HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

PDF	16 Pages

Scroll/Zoom	100%

nhà sản xuất	IDT [Integrated Device Technology]

Trang chủ	http://www.idt.com

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IDT7132SA/LA and IDT 7142SA/LA

High Speed 2K x 8 Dual Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write with BUSY(4)

NOTES:

1. tWH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB applies only to the slave version (IDT7142).

4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".

Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)

BUSY"B"

2692 drw 12

W"A"

tWP

tWH

(1)

tWB

W"B"

(2)

(3)

tWC

tWP

tDW

tDH

tBDD

tDDD

tBDA

tWDD

ADDR"B"

DATAOUT"B"

DATAIN"A"

ADDR"A"

MATCH

VALID

MATCH

VALID

W"A"

BUSY"B"

tAPS

(1)

2692 drw 11

tBAA

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".

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