 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
IDT7133LA55GB bảng dữ liệu(PDF) 10 Page - Integrated Device Technology |
|
|
|||||||||||||||||||||||||||||
IDT7133LA55GB bảng dữ liệu(HTML) 10 Page - Integrated Device Technology |
|
|
10 / 16 page  6.42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges 10 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(6) NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy". 2. tBDD is calculated parameter and is greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual). 3. To ensure that the earlier of the two ports wins. 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part number indicates power rating (SA or LA). 7133X20 7143X20 Com'l Only 7133X25 7143X25 Com'l, Ind & Military 7133X35 7143X35 Com'l, Ind & Military Symbol Parameter Min.Max. Min.Max.Min.Max. Unit BUSY TIMING (For MASTER 71V33) tBAA BUSY Access Time from Address ____ 20 ____ 20 ____ 30 ns tBDA BUSY Disable Time from Address ____ 20 ____ 20 ____ 30 ns tBAC BUSY Access Time from Chip Enable ____ 20 ____ 20 ____ 25 ns tBDC BUSY Disable Time from Chip Enable ____ 17 ____ 20 ____ 25 ns tWDD Write Pulse to Data Delay (1) ____ 40 ____ 50 ____ 60 ns tDDD Write Data Valid to Read Data Delay (1) ____ 30 ____ 35 ____ 45 ns tBDD BUSY Disable to Valid Data(2) ____ 25 ____ 30 ____ 35 ns tAPS Arbitration Priority Set-up Time (3) 5 ____ 5 ____ 5 ____ ns tWH Write Hold After BUSY(5) 20 ____ 20 ____ 25 ____ ns BUSY INPUT TIMING (For SLAVE 71V43) tWB BUSY Input to Write(4) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 20 ____ 20 ____ 25 ____ ns tWDD Write Pulse to Data Delay (1) ____ 40 ____ 50 ____ 60 ns tDDD Write Data Valid to Read Data Delay (1) ____ 30 ____ 35 ____ 45 ns 2746 tbl 12a 7133X45 7143X45 Com'l & Military 7133X55 7143X55 Com'l, Ind & Military 7133X70/90 7143X70/90 Com'l & Military Symbol Parameter Min.Max. Min.Max.Min.Max. Unit BUSY TIMING (For MASTER 71V33) tBAA BUSY Access Time from Address ____ 40 ____ 40 ____ 45/45 ns tBDA BUSY Disable Time from Address ____ 40 ____ 40 ____ 45/45 ns tBAC BUSY Access Time from Chip Enable ____ 30 ____ 35 ____ 35/35 ns tBDC BUSY Disable Time from Chip Enable ____ 25 ____ 30 ____ 30/30 ns tWDD Write Pulse to Data Delay (1) ____ 80 ____ 80 ____ 90/90 ns tDDD Write Data Valid to Read Data Delay (1) ____ 55 ____ 55 ____ 70/70 ns tBDD BUSY Disable to Valid Data(2) ____ 40 ____ 40 ____ 40/40 ns tAPS Arbitration Priority Set-up Time (3) 5 ____ 5 ____ 5/5 ____ ns tWH Write Hold After BUSY(5) 30 ____ 30 ____ 30/30 ____ ns BUSY INPUT TIMING (For SLAVE 71V43) tWB BUSY Input to Write(4) 0 ____ 0 ____ 0/0 ____ ns tWH Write Hold After BUSY(5) 30 ____ 30 ____ 30/30 ____ ns tWDD Write Pulse to Data Delay (1) ____ 80 ____ 80 ____ 90/90 ns tDDD Write Data Valid to Read Data Delay (1) ____ 55 ____ 55 ____ 70/70 ns 2746 tbl 12b |
|
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
