IDT7133LA55JB datasheet(12/16 Pages) IDT

tên linh kiện	IDT7133LA55JB

Giải thích chi tiết về linh kiện	HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS

PDF	16 Pages

Scroll/Zoom	100%

nhà sản xuất	IDT [Integrated Device Technology]

Trang chủ	http://www.idt.com

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12 / 16 page

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

2746 drw 11

tDW

tAPS

ADDR"A"

tWC

MATCH

tWP

W"A"

DATAIN"A"

ADDR"B"

tDH

VALID

(1)

MATCH

BUSY"B"

tBDA

VALID

tBDD

tDDD

(4)

tWDD

DATAOUT "B"

Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3)

Timing Waveform of Write with BUSY(3)

NOTES:

1. tWH must be met for both

BUSY input (IDT7143, slave) and output (IDT7133, master).

BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

NOTES:

1. To ensure that the earlier of the two ports wins, tAPS is ignored for Slave (IDT7143).

CEL = CER = VIL

OE = VIL for the reading port.

4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

2746 drw 12

W"A"

BUSY"B"

tWP

tWB

W"B"

tWH

(1)

(2)

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