3

ICS9250-26

Maximum Allowed Current

E

0

1

8

n

o

i

t

i

d

n

o

C

n

o

i

t

p

m

u

s

n

o

c

y

l

p

p

u

s

V

5

.

2

x

a

M

,

s

d

a

o

l

p

a

c

e

t

e

r

c

s

i

d

x

a

M

V

5

2

6

.

2

=

2

q

d

d

V

D

N

G

r

o

3

q

d

d

V

=

s

t

u

p

n

i

c

i

t

a

t

s

l

l

A

n

o

i

t

p

m

u

s

n

o

c

y

l

p

p

u

s

V

5

.

2

x

a

M

,

s

d

a

o

l

p

a

c

e

t

e

r

c

s

i

d

x

a

M

V

5

6

4

.

3

=

2

q

d

d

V

D

N

G

r

o

3

q

d

d

V

=

s

t

u

p

n

i

c

i

t

a

t

s

l

l

A

e

d

o

M

n

w

o

d

r

e

w

o

P

0

=

#

N

W

D

R

W

P

(

A

m

0

1A

m

0

1

z

H

M

6

6

e

v

i

t

c

A

l

l

u

F

0

1

=

0

,

1

L

E

S

A

m

0

7A

m

0

8

2

z

H

M

0

0

1

e

v

i

t

c

A

l

l

u

F

1

1

=

0

,

1

L

E

S

A

m

0

0

1A

m

0

8

2

Clock Enable Configuration

#

D

PK

L

C

U

P

CM

A

R

D

SC

I

P

A

O

Iz

H

M

6

6K

L

C

I

C

P

,

F

E

R

z

H

M

8

4

c

s

Os

O

C

V

0W

O

LW

O

LW

O

LW

O

LW

O

LW

O

LF

F

OF

F

O

1N

ON

ON

ON

ON

ON

ON

ON

O

Power Groups*

VDD0, GND0 = REF & Crystal

VDD1, GND1 = 3V66

VDD2, GND2 = PCICLK

VDD3, GND3 = PLL core

VDD4, GND4 = 48MHz

VDD5, GND5 = SDRAM_F, SDRAM

VDDL0, GNDL0 = CPUCLK

VDDL1, GNDL1 = IOAPIC

* To ensure the processor will power up to the desired frequency, the 3.3V supply to the ICS9250-26 needs to reach a stable

condition before the 2.5V supply does. In most systems, the power up ramp of the 2.5V is slower than the 3.3V ramp. For those

instances, no special requirements are necessary.