Integrated

Circuit

Systems, Inc.

ICS9250-22

Third party brands and names are the property of their respective owners.

9250-22 Rev B 12/08/00

Pin Configuration

56-Pin 300mil SSOP & TSSOP

Recommended Application:

P IV Chipset Support

Output Features:

•

4 Differential CPU Clock Pairs @ 3.3V

•

2 - 3V MREF clocks for memory reference seeds,

(separate single ended but 180 degrees out of phase)

•

4 - 66MHz reference output

•

10 - 3V 33MHz PCI clocks

•

2 - 48MHz clocks

•

2 - 14.318 reference output

Features:

•

Support power management: Power Down Mode

•

Supports Spread Spectrum modulation: 0 to -0.5% down

spread.

•

Uses external 14.318MHz crystal

•

Select logic for Differential Swing Control, Test mode,

Tristate, Power down, Spread Spectrum, limited

frequency select, selective clock enable.

•

External resistor for current reference

•

FS pins for frequency select

Key Specifications:

•

3V66 Output jitter <300ps

•

CPU Output Jitter <200ps

•

MREF Output jitter <250ps

Frequency Generator for P IV™

GND

REF

VDDREF

X1

X2

GNDREF

PCICLK0

PCICLK1

VDDPCI

PCICLK2

PCICLK3

GNDPCI

PCICLK4

PCICLK5

VDDPCI

PCICLK6

PCICLK7

GNDPCI

PCICLK8

PCICLK9

VDDPCI

SEL100/133

GND48

48MHz

48MHz

VDD48

PD#

MULTSEL0/

MULTSEL1/REF

FS0/

FS1/

VDDMREF

3VMREF

3VMREF_B

GNDMREF

SPREAD#

CPUCLKST3

CPUCLKSC3

VDDCPU

CPUCLKST2

CPUCLKSC2

GNDCPU

CPUCLKST1

CPUCLKSC1

VDDCPU

CPUCLKST0

CPUCLKSC0

GNDCPU

I REF

VDDA

GNDA

VDD3V66

3V66-3

3V66-2

GND3V66

GND3V66

3V66-1

3V66-0

VDD3V66

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

Functionality

PLL2

PLL1

Spread

Spectrum

48MHz

3VMREF

PCICLK (9:0)

3VMREF_B

3V66 (3:0)

4

10

2

2

X1

X2

XTAL

OSC

CPU

DIVDER

3VMREF

DIVDER

PCI

DIVDER

3V66

DIVDER

PD#

SPREAD#

MULTSEL (1:0)

SEL100/133

FS(1:0)

Control

Logic

Config.

Reg.

REF

4

4

CPUCLKST (3:0)

CPUCLKSC (3:0)

/

3

3

1

L

E

S

0

0

1

0

S

F1

S

Fn

o

i

t

c

n

u

F

00

0

z

H

M

0

0

1

e

v

i

t

c

A

00

1

)

d

e

v

r

e

s

e

R

(

01

0

)

d

e

v

r

e

s

e

R

(

01

1

s

t

u

p

t

u

o

l

l

a

e

t

a

t

s

i

r

T

10

0

z

H

M

3

3

1

e

v

i

t

c

A

10

1

)

d

e

v

r

e

s

e

R

(

11

0

)

d

e

v

r

e

s

e

R

(

11

1

e

d

o

M

t

s

e

T

Block Diagram

Power Groups

VDDREF, GNDREF= REF, X1, X2

VDDPCI, GNDPCI = PCICLK

VDD48, GND48 = 48MHz, PLL2

VDD3V66, GND3V66=3V66

VDDCPU, GNDCPU = CPUCLK

VDDMREF, GNDMREF=3VMREF, 3VMREF_B

VDDA=VDD (core supply voltage 3.3V)

GNDA=Ground for core supply

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.