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ICS9250-12 bảng dữ liệu(PDF) 3 Page - Integrated Circuit Systems

tên linh kiện ICS9250-12
Giải thích chi tiết về linh kiện  Frequency Timing Generator for PENTIUM II/III Systems
PDF  12 Pages
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nhà sản xuất  ICST [Integrated Circuit Systems]
Trang chủ  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS9250-12 bảng dữ liệu(HTML) 3 Page - Integrated Circuit Systems

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3
ICS9250-12
Frequency Select:
Note:
1. TCLK is a test clock driven on the x1 input during test mode.
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ICS9250-12 Power Management Features:
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
4.All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW.
5. CPU/2, IOAPIC, REF, 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions
except PD# = LOW
Power Groups:
VDDREF,GNDREF=REF,X1,X2
GNDPCI,VDDPCI=PCICLK
VDD66,GND66=3V66
VDD48,GND48=48MHz
VDDCOR,GNDCOR=PLLCore
VDDLCPU/2,GNDLCPU/2=CPU/2
VDDLIOAPIC,GNDIOAPIC=IOAPIC
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