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ICS9248-92 bảng dữ liệu(PDF) 13 Page - Integrated Circuit Systems |
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ICS9248-92 bảng dữ liệu(HTML) 13 Page - Integrated Circuit Systems |
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13 / 14 page ![]() 13 ICS9248-92 Connections to VDD: General Layout Precautions: 1) Use a ground plane on the top routing layer of the PCB in all areas not used by traces. 2) Make all power traces and ground traces as wide as the via pad for lower inductance. Notes: 1 All clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. Not shown in all places to improve readability of diagram. 2 Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed. Component Values: C1 : Crystal load values determined by user C2 : 22F/20V/D case/Tantalum AVX TAJD226M020R C3 : 15pF capacitor FB = Fair-Rite products 2512066017X1 All unmarked capacitors are 0.01F ceramic 3.3V Power Route 3.3V Power Route 2.5V Power Route C3 C1 C1 C4 1 Clock Load 2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Ferrite Bead VDD C2 22µF/20V Tantalum Ferrite Bead VDD C2 22µF/20V Tantalum 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 = Routed Power = Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load |
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