2

ICS9248-107

Pin Descriptions

The ICS9248-107 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip

provides all the clocks required for such a system when used with a zero delay buffer such as the ICS9179-06.

Spread Spectrum may be enabled through I

EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-107 employs a proprietary

closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

General Description

Pin number

Pin name

Type

Description

1, 7, 13, 19, 25, 31 GND

PWR

Ground pins

2

REF0

OUT

14.318MHz reference clock outputs at 3.3V

REF1

OUT

14.318MHz reference clock outputs at 3.3V

SEL24_48#

IN

Logic input to select 24 or 48MHz for pin 26 output

4, 10, 16, 23,

28, 35

VDD

PWR

Power pins 3.3V

5

X1

IN

XTAL_IN 14.318MHz crystal input

6

X2

OUT

XTAL_OUT Crystal output

PCICLK_F

OUT

Free running PCI clock at 3.3V. Synchronous to CPU clocks.

FS0

IN

Logic - input for frequency selection

PCICLK1

OUT

PCI clock output at 3.3V. Synchronous to CPU clocks.

FS1

IN

Logic - input for frequency selection

PCICLK2

OUT

PCI clock output at 3.3V. Synchronous to CPU clocks.

FS2

IN

Logic - input for frequency selection

PCICLK3

OUT

PCI clock output at 3.3V. Synchronous to CPU clocks.

FS3

IN

Logic - input for frequency selection

14, 15, 17, 18, 20,

21, 22

PCICLK (4:10)

OUT

PCI clock outputs at 3.3V. Synchronous to CPU clocks.

24

PD#

IN

This asynchronous input powers down the chip when drive

active(Low). The internal PLLs are disabled and all the output clocks

are held at a Low state.

26

24_48MHz

OUT

24 or 48MHz output selectable by

SEL24_48# (0=48MHz 1=24MHz)

48MHz

OUT

Fixed 48MHz clock output at 3.3V

FS4

IN

Logic - input for frequency selection

29

SCLK

IN

Clock input of I

2

C input

30

SDATA

I/O

Data pin for I2C circuitry 5V tolerant

32, 33, 34

3V66(2:0)

OUT

3.3V clock outputs.

36, 41

GNDLCPU

PWR

Ground pins for CPUCLKs

37, 38, 40, 42

CPUCLK(3:0)

OUT

Host bus clock output at 2.5V.

39, 43

VDDLCPU

PWR

Power pins for CPUCLKs. 2.5V

45

GNDLAPIC

PWR

Ground pin for the IOAPIC outputs.

44, 46, 47

IOAPIC(2:0)

OUT

IOAPIC clocks at 2.5V. Synchronous with CPUCLKs.

48

VDDLAPIC

PWR

Power pin for the IOAPIC outputs. 2.5V.

27

12

3

8

9

11