ICS9150F-04 datasheet(5/19 Pages) ICST

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ICS9150-04

VDD(1,2,3,4)

This is the power supply to the internal core logic of the

device as well as the clock output buffers for REF, PCICLK,

and SDRAM.

This pin operates at 3.3V volts. Clocks from the listed buffers

that it supplies will have a voltage swing from Ground to this

level. For the actual guaranteed high and low voltage levels

for the Clocks, please consult the DC parameter table in this

data sheet.

VDDL1,2

This is the power supply for the CPUCLK and IOAPIC output

buffers. The voltage level for these outputs may be 2.5 or

3.3volts. Clocks from the buffers that each supplies will have

a voltage swing from Ground to this level. For the actual

Guaranteed high and low voltage levels of these Clocks,

please consult the DC parameter table in this Data Sheet.

GND

This is the power supply ground (common or negative) return

pin for the internal core logic and all the output buffers.

This input pin serves one of two functions. When the device

is used with a Crystal, X1 acts as the input pin for the

reference signal that comes from the discrete crystal. When

the device is driven by an external clock signal, X1 is the

device input pin for that reference clock. This pin also

implements an internal Crystal loading capacitor that is

connected to ground. With nominal value of 33pF no external

load cap is needed for a CL=17 to 18pF crystal.

This Output pin is used only when the device uses a Crystal

as the reference frequency source. In this mode of operation,

X2 is an output signal that drives (or excites) the discrete

Crystal. The X2 pin will also implement an internal Crystal

loading capacitor that is nominally 33pF.

CPUCLK (0:4)

These Output pins are the Clock Outputs that drive processor

and other CPU related circuitry that requires clocks which are

in tight skew tolerance with the CPU clock. The voltage

swing of these Clocks is controlled by the Voltage level

applied to the VDDL2 pin of the device. See the Functionality

Table for a list of the specific frequencies that are available

for these Clocks and the selection codes to produce them.

SDRAM(0:15)

These Output Clocks are used to drive Dynamic RAMs and

are low skew copies of the CPU Clocks. The voltage swing of

the SDRAMs output is controlled by the supply voltage

that is applied to VDD3 of the device. Operates at 3.3 volts.

IOAPIC (0:2)

These Outputs are fixed frequency Output Clocks that run at

the Reference Input frequency (typically 14.31818MHz) . Its

voltage level swing is controlled by VDDL1 and may operate

at 2.5 or 3.3volts.

REF0

The REF Output is a fixed frequency Clock that runs at the

same frequency as the Input Reference Clock X1 or the

Crystal (typically 14.31818MHz) attached across X1 and X2.

Technical Pin Function Descriptions

PCICLK_F

This Output is equal to PCICLK(0:5). It is FREE RUNNING, and

will not be stopped by PCI_STOP#.

PCICLK (0:5)

These Output Clocks generate all the PCI timing requirements

for a Pentium/Pro based system. They conform to the current

PCI specification. They run at 1/2 CPU frequency, for most

choices of FS (0:2).

FS(0:2)

These Input pins control the frequency of the Clocks at the

CPU, PCICLK and SDRAM output pins. These inputs are

Bidirectional Input/Output pins, latched at internal power-on-

reset.

MODE

This Input pin is used to select the Input function of the I/O

pins. An active Low will place the I/O pins in the Input mode

and enable the stop clock functions. (This is the Power

Management Mode)

CPU_STOP#

This is a synchronous active Low Input pin used to stop the

CPUCLK clocks in an active low state. All other Clocks including

SDRAM clocks will continue to run while this function is

enabled. The CPUCLKs will have a turn ON latency of at least

3 CPU clocks. This input pin valid only when MODE=0 (Power

Management Mode)

PCI_STOP#

This is a synchronous active Low Input pin used to stop the

PCICLK clocks in an active low state. It will not effect PCICLK_F

nor any other outputs. This input pin valid only when MODE=0

(Power Management Mode)

I2C (SDATA, SCLK)

The SDATA and SCLOCK Inputs are use to program the device.

The clock generator is a slave-receiver device in the I2C

protocol. It will allow read-back of the registers. See

configuration map for register functions. The I2C specification

in Philips I2C Peripherals Data Handbook (1996) should be

followed.

48MHz

This is a fixed frequency Clock output at 48MHz that is typically

used to drive USB devices.

24MHz

This pin is a fixed frequency clock output typically used to

drive Super I/O devices.

CPU 3.3#_2.5

This Input pin controls the CPU output buffer strength for

skew matching CPU and SDRAM outputs to compensate for

the external VDDL supply condition. It is important to use this

function when selecting power supply requirements for

VDDL1,2. A logic 1 (ground) will indicate 2.5V operation and

a logic 0 will indicate 3.3V operation. This pin has an internal

pullup resistor to VDD.

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