7

ICS9150-01

Power Management

ICS9150-01 Power Management Requirements

Clock Enable Configuration

Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. The first clock

pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing

and signal loading may have a large impact on the initial clock distortion also.

Notes.

1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.

2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.

Byte 5: Peripheral Clock Register

Notes: 1 = Enabled; 0 = Disabled, outputs held low

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

ti

B-

1

d

e

v

r

e

s

e

R

6

ti

B2

1

)

t

c

a

n

I

/t

c

A

(

2

C

I

P

A

O

I

5

ti

B4

51

)

t

c

a

n

I

/t

c

A

(

1

C

I

P

A

O

I

4

ti

B5

51

)

t

c

a

n

I

/t

c

A

(

0

C

I

P

A

O

I

3

ti

B-

1

d

e

v

r

e

s

e

R

2

ti

B-

1

d

e

v

r

e

s

e

R

1

ti

B-

1

d

e

v

r

e

s

e

R

0

ti

B3

1

)

t

c

a

n

I

/t

c

A

(

0

F

E

R

#

P

O

T

S

_

U

P

C#

P

O

T

S

_

I

C

PK

L

C

U

P

CK

L

C

I

C

P

,

s

k

c

o

l

C

r

e

h

t

O

,

M

A

R

D

S

,

F

E

R

s

C

I

P

A

O

I

l

a

t

s

y

r

Cs

O

C

V

00

w

o

Lw

o

Lg

n

i

n

n

u

Rg

n

i

n

n

u

Rg

n

i

n

n

u

R

01

w

o

Lz

H

M

0

3

/

3

.

3

3g

n

i

n

n

u

Rg

n

i

n

n

u

Rg

n

i

n

n

u

R

10

z

H

M

0

6

/

6

.

6

6w

o

Lg

n

i

n

n

u

Rg

n

i

n

n

u

Rg

n

i

n

n

u

R

11

z

H

M

0

6

/

6

.

6

6z

H

M

0

3

/

3

.

3

3g

n

i

n

n

u

Rg

n

i

n

n

u

Rg

n

i

n

n

u

R

L

A

N

G

I

SE

T

A

T

S

L

A

N

G

I

S

y

c

n

e

t

a

L

g

n

i

n

n

u

r

e

e

r

f

f

o

s

e

g

d

e

g

n

i

s

i

r

f

o

.

o

N

K

L

C

I

C

P

#

P

O

T

S

_

U

P

C

)

d

e

l

b

a

s

i

D

(

0

2

1

)

d

e

l

b

a

n

E

(

1

1

1

#

P

O

T

S

_

I

C

P

)

d

e

l

b

a

s

i

D

(

0

2

1

)

d

e

l

b

a

n

E

(

1

1

1

Byte 6: Optional Register for Future

Notes:

1. Byte 6 is reserved by Integrated Circuit Systems for

future applications.

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

ti

B-

1

d

e

v

r

e

s

e

R

6

ti

B-

1

d

e

v

r

e

s

e

R

5

ti

B-

1

d

e

v

r

e

s

e

R

4

ti

B-

1

d

e

v

r

e

s

e

R

3

ti

B-

1

d

e

v

r

e

s

e

R

2

ti

B-

1

d

e

v

r

e

s

e

R

1

ti

B-

1

d

e

v

r

e

s

e

R

0

ti

B-

1

d

e

v

r

e

s

e

R