ICS650-14B

Networking System Clock

MDS 650-14B A

3

Revision 082800

Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com

PRELIMINARY INFORMATION

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (n

note 1)

Supply voltage, VDD

Referenced to GND

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

°C

Ambient Operating Temperature

Industrial "I" version

-40

85

°C

Soldering Temperature

Max of 20 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 3.3V

V unless noted)

Operating Voltage, VDD

3

5.5

V

Input High Voltage, VIH, X1 pin only

Clock Input

VDD/2 + 1

V

Input Low Voltage, VIL, X1 pin only

Clock Input

VDD/2 - 1

V

Input High Voltage, VIH, SEL pins only

VDD - 0.5

V

Input Low Voltage, VIL, SEL pins only

0.5

V

Input High Voltage, VIH, OE pin only

2.0

V

Input Low Voltage, VIL, OE pin only

0.8

V

Output High Voltage, VOH

IOH=-12mA

2.4

V

Output Low Voltage, VOL

IOL=12mA

0.4

V

Output High Voltage, VOH, CMOS level

IOH=-8mA

VDD-0.4

V

Operating Supply Current, IDD

No Load

TBD

mA

Short Circuit Current

Each output

±50

mA

AC CHARACTERISTICS (VDD = 3.3V

V unless noted)

Input Frequency

25.000

MHz

Output Clock Rise Time

0.8 to 2.0V

1.5

ns

Output Clock Fall Time

2.0 to 0.8V

1.5

ns

Output Clock Duty Cycle

At VDD/2

45

50

55

%

Frequency error

All clocks

0

ppm

Absolute Jitter, short term

Variation from mean

TBD

ps

Electrical Specifications

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

2. CMOS level input, nominal trip point is VDD/2 for 3.3 V or 5 V operation.

External Components

The ICS650R-14B requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.01µF should be connected between each VDD and GND on Pins 4 and 6, and Pins 16 and

14, as close to the ICS650R-14B as possible. A series termination resistor of 33

Ω may be used for each

clock output. The 25.00 MHz crystal must be connected as close to the chip as possible. The crystal should

be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be

connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these