ICS650-05

HDTV Clock Synthesizer

MDS 650-05 A

2

Revision 081199

Printed 12/4/00

Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax

PRELIMINARY

INFORMATION

Pin #

Name

Type

Description

1

VDD

P

Connect to +3.3 V or +5.0 V. Must be same as other VDDs.

2

X2

XO

Crystal connection to a 27.0 MHz crystal or leave unconnected for clock input

3

X1/ICLK

XI

Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input.

4

VDD

P

Connect to +3.3 V or +5.0 V. Must be same as other VDDs.

5

VDD

P

Connect to +3.3 V or +5.0 V. Must be same as other VDDs.

6

GND

P

Connect to ground.

7

NC

-

No Connect. Do not connect anything to this pin.

8

27M

O

27 MHz buffered oscillator clock output.

9

13.5M

O

13.5 MHz clock output.

10

GND

P

Connect to ground.

11

GND

P

Connect to ground.

12

27M

O

27 MHz buffered clock output.

13

54M

O

54 MHz buffered clock output.

14

GND

P

Connect to ground.

15

GND

P

Connect to ground.

16

VDD

P

Connect to +3.3 V or +5.0 V. Must be same as other VDDs.

17

FRCLK

O

Frame Rate Clock as shown on table.

18

FRS

I

Frame Rate Frequency Select input pin. Determines FRCLK output as shown on table.

19

OE

I

Output Enable. Tri-states all clocks when low.

20

VDD

P

Connect to +3.3 V or +5.0 V. Must be same as other VDDs.

Pin Descriptions

Key: I = Input with internal pull-up; O = output; P = power supply connection; XI, XO = crystal

connections

1

16

2

3

4

15

14

13

VDD

NC

X2

VDD

20 pin SSOP (QSOP)

5

6

7

8

12

11

10

9

GND

OE

X1/ICLK

VDD

FRS

VDD

FRCLK

27M

GND

13.5M

27M

18

17

19

20

GND

VDD

54M

GND

GND

Pin Assignment

FRCLK Output Select Table (in MHz)

FRS Pin 18

FRCLK Pin 17

0

74.175824

1

74.250000