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ICS554-01 bảng dữ liệu(PDF) 1 Page - Integrated Circuit Systems |
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ICS554-01 bảng dữ liệu(HTML) 1 Page - Integrated Circuit Systems |
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1 / 5 page ![]() ICS554-01 MDS 554-01 A 1 Revision 031901 In tegr ated C i r cu i t S y st ems G 5 25 Ra ce Str eet, San Jose, C A 95 126 G tel ( 408) 2 95-9 800 G w w w.ic s t .c o m LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT PRE L IMINAR Y INF O RMA T IO N Description The ICS554-01 is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL clock buffer. For parts which do not require PECL inputs or outputs, see the ICS553 for a 1 to 4 low skew buffer, or the ICS552-02 for a 1 to 8 low skew buffer. For more than 8 outputs see the MK74CBxxx BuffaloTM series of clock drivers. ICS makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs. Features • Outputs are skew matched to within 50ps • Packaged in 16 pin TSSOP • One PECL input to 4 PECL output clock drivers • Operating Voltages of 3.3V to 5V Block Diagram IN IN RES VDD 0.01mF 1.1k Ω Q0 Q0 VDD 62Ω 62Ω 270Ω 270Ω Q1 Q1 VDD 62Ω 62 Ω 270Ω 270Ω Q2 Q2 VDD 62Ω 62Ω 270Ω 270Ω Q3 Q3 VDD 62Ω 62Ω 270Ω 270Ω |
Số phần tương tự - ICS554-01 |
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Mô tả tương tự - ICS554-01 |
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