ICS1523MLFT datasheet(1/21 Pages) ICST

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MDS 1523 Y

1

Revision 110905

Integrated Circuit Systems

525 Race Street, San Jose, CA 95126

tel (408) 297-1201

www.icst.com

Video Clock Synthesizer with I2C Programmable Delay

ICS1523

Features

• Low Jitter

• Wide input frequency range

• 15.734 kHz to 100 MHz

• PECL differential outputs

• Up to 250 MHz

• SSTL_3 Single-ended clock outputs

• Up to 150 MHz

• Dynamic Phase Adjust (DPA) for all outputs

• I2C controlled phase adjustment

• Full clock cycle down to 1/64 of a clock

• Double-buffered control registers

• External or internal loop filter selection

• COAST input can disable charge pump

• 3.3 VDD

• 5 volt Tolerant Inputs

• Industry Standard I2C-bus programming interface

• PLL Lock detection via I2C or LOCK/REF output pin

• 24-pin 300-mil SOIC package

• Available in Pb-free packaging

Applications

• Frequency synthesis

• LCD monitors, video projectors and plasma displays

• Genlocking multiple video subsystems

Pin Configuration

24-pin SOIC

General Description

The ICS1523 is a low-cost, high-performance

frequency generator. It is well suited to general

purpose phase controlled clock synthesis as well as

line-locked and genlocked high-resolution video

applications. Using ICS’s advanced low-voltage

CMOS mixed-mode technology, the ICS1523 is an

effective phase controlled clock synthesizer and also

supports video projectors and displays at resolutions

from VGA to beyond UXGA.

The ICS1523 offers clock outputs in both differential

(to 250 MHz) and single-ended (to 150 MHz) formats.

Dynamic Phase Adjust (DPA) allows I2C™ control of

the output clock’s phase relative to the input sync

signal. A second, half speed set of outputs that can be

separately enabled allows such applications as

clocking analog-to-digital converters. The FUNC pin

provides either the regenerated input from the

phase-locked loop (PLL) divider chain output, or the

input HSYNC after being sharpened by the Schmitt

trigger. Both signals are then delayed by the DPA.

The advanced PLL uses either its internal

programmable feedback divider or an external divider.

Either the internal or external loop filters is software

selectable. The COAST input pin disables the PLL’s

charge pump, causing the device to idle at the current

speed for short periods of time, such as vertical

blanking intervals.

The device is programmed by a standard I2C-bus

serial interface and is available in a 24-pin, wide

small-outline integrated circuit (SOIC) package.

ICS1523 Functional Diagram

OSC

External Loop Filter (optional)

CLK/2

FUNC

CLK

I C I/F

2

HSYNC

Số phần tương tự - ICS1523MLFT

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