ICS1531 datasheet(66/76 Pages) ICST

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ICS1531 Rev N 12/1/99

December, 1999

Chapter 10

Timing Diagrams

ICS1531 Data Sheet - Preliminary

10.2

Power-On Reset Timing

Table 10-2 lists typical ICS1531 power-on reset (POR) timing measures and Figure 10-4 shows the POR

timing relationships. (For information on how the ICS1531 POR circuitry operates, see Section 8.2, “Power

Considerations”.)

If a reset:

• Is desired, reduce the VDD supply voltage (and the voltage on all ICS1531 pins) so that it is below the

threshold voltage (VDDth) of the POR circuit for the period t1. (A time of 10 ms is sufficient.)

• Is not desired, ensure either one or both of the following conditions:

– Ensure the VDD supply voltage (and the voltage on all ICS1531 pins) is not reduced below Vmin.

– If the VDD supply voltage (and the voltage on all ICS1531 pins) is reduced below Vth, then ensure

that it is at this level for less than the period t1.

Note:

The POR signal is an internal signal. It is generated regardless of the ICS1531 mode.

Figure 10-4.

Power-On Reset Condition for ICS1531

Table 10-2.

Typical ICS1531 POR Transition Times

Symbol

Timing Description

Min

Typ

Max

Units

VDD

Supply Voltage (‘On’ State)

3.0

3.3

3.6

VDDth

Threshold Supply Voltage

–

1.8

–

Hold Time for Reset State

–

VDDth

VDDmin

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