4

AV9110

Serial Programming

The AV9110 is programmed to generate clock frequencies by

entering data through the shift register. Figure 1 displays the

proper timing sequence. On the negative going edge of CE#,

the shift register is enabled and the data at the DATA pin is

loaded into the shift register on the rising edge of the SCLK.

Bit D0 is loaded first, followed by D1, D2, etc. This data

consists of the 24 bits shown in the Shift Register Bit

Assignment in Table 1, and therefore takes 24 clock cycles to

load. An internal counter then disables the input and transfers

the data to internal latches on the rising edge of the 24th

cycle of the SCLK. Any data entered after the 24th cycle is

ignored until CE# must remain low for a minimum of 24 SLCK

clock cycles. If CE# is taken high before 24 clock cycles have

elapsed, the data is ignored (no frequency change occurs)

and the counter is reset. Tables 1 and 2 display the bit location

for generating the output clock frequency and the output

divider circuitry, respectively.

T

I

BT

N

E

M

N

G

I

S

S

A

N

O

I

T

A

U

Q

E

E

L

B

A

I

R

A

V

T

L

U

A

F

E

D

T

I

B

1

0

-2

0

-

0)

B

S

L

(

r

e

d

i

v

i

d

y

c

n

e

u

q

e

r

f

O

C

V

N

r

e

g

e

t

n

I

M

r

e

g

e

t

n

I

11

0

1r

e

d

i

v

i

d

y

c

n

e

u

q

e

r

f

O

C

V

111

2r

e

d

i

v

i

d

y

c

n

e

u

q

e

r

f

O

C

V

11

2

3r

e

d

i

v

i

d

y

c

n

e

u

q

e

r

f

O

C

V

11

3

4r

e

d

i

v

i

d

y

c

n

e

u

q

e

r

f

O

C

V

11

4

5r

e

d

i

v

i

d

y

c

n

e

u

q

e

r

f

O

C

V

11

5

6)

B

S

M

(

r

e

d

i

v

i

d

y

c

n

e

u

q

e

r

f

O

C

V

11

6

7)

B

S

L

(

r

e

d

i

v

i

d

y

c

n

e

u

q

e

r

f

e

c

n

e

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f

e

R

00

7

8r

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d

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c

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e

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q

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f

e

c

n

e

r

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f

e

R

11

8

9r

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d

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d

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c

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u

q

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f

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c

n

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f

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R

00

9

0

1r

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d

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c

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q

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0

1

1

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11

1

1

2

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R

00

2

1

3

1)

B

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c

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q

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c

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f

e

R

00

3

1

4

1

V

8

y

b

e

d

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v

i

d

=

1

,

1

y

b

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d

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=

0

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p

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00

4

1

5

1

)

2

e

l

b

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(

0

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01

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11

9

1

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11

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2

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c

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1

(

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2

2

3

2)

1

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d

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R

11

3

2