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HM6P5331 bảng dữ liệu(PDF) 4 Page - Hynix Semiconductor

tên linh kiện HM6P5331
Giải thích chi tiết về linh kiện  HM6P5331 - 2.0GHz/500MHz Dual Frequency Synthesizer
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HM6P5331 bảng dữ liệu(HTML) 4 Page - Hynix Semiconductor

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PRELIMINARY

Absolute Maximum Ratings
Power Supply Voltage
VDD
-0.3V to +4.2V
VPP
-0.3V to +4.2V
Voltage on Any Pin
with GND = 0V (V
I)
-0.3V to +4.2V
Storage Temperature Range (T
S)
-65
°C to +150°C
Lead Temperature (solder 4 sec.) (T
L)
260
°C
Thermal Resistance(Typical)
θ
JA (°C/W)
TSSOP Package
130
°C
Operating Conditions
Power Supply Voltage
VDD
2.7V to 3.6V
VPP
VDD to 3.6V
Operating Temperature(T
A)
-40
°C to 85°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Other conditions
above those indicated in the operational sections of this specification are not implied.
Electrical Characteristics
VDD = 3.0V, -40
°C < T
A < 85°C, Except as Specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RF
VDD=2.7V to 3.6V,
fΦ= 10KHz
3.2
mA
I
DD
Power Supply Current
IF
VDD=2.7V to 3.6V,
fΦ= 10KHz
1.2
5.4
mA
I
DD-PWDN
Powerdown Current
V
DD=3.0V
110
µA
f
INRF
Operating Frequency
0.5
-
2.0
GHz
f
INIF
Operating Frequency
50
-
500
MHz
f
OSC
Oscillator Frequency.
4
-
40
MHz
fΦ
Maximum Phase Detector Freq.
10
-
-
MHz
Pf
INRF
RF Input Sensitivity
V
DD=2.7V to 3.6V
- 8.5
-
0
dBm
Pf
INIF
IF Input Sensitivity
V
DD=2.7V to 3.6V
-10
-
0
dBm
V
OSC
Oscillator Sensitivity
OSC
IN
0.5
-
-
V
PP
V
IH
High Level Input Voltage
*
0.8 V
DD
--
V
V
IL
Low Level Input Voltage
*
-
-
0.2 V
DD
V
I
IH
High Level Input Current
V
IH =VDD=3.6V*
-1.0
-
1.0
µA
I
IL
Low Level Input Current
V
IL =0V, VDD=3.6V*
-1.0
-
1.0
µA
I
IH
Oscillator Input Current
V
IH =VDD=3.6V
-
-
100
µA
I
IL
Oscillator Input Current
V
IL =0V, VDD=3.6V
-100
-
-
µA
V
OH
High-Level Output Voltage
I
OH = -500 µA
V
DD-0.4
-
-
V
V
OL
Low-Level Output Voltage
I
OL = 500 µA
--
0.4
V
t
CS
Data Clock Setup Time
See Data Input Timing
50
-
-
ns
t
CH
Data Clock Hold Time
See Data Input Timing
10
-

t
CWH
Clock Pulse Width High
See Data Input Timing
50
-
-

t
CWL
Clock Pulse Width Low
See Data Input Timing
50
-
-

t
ES
Clock to Load Enable Setup Time
See Data Input Timing
50
-
-

t
EW
Load Enable Pulse Width
See Data Input Timing
50
-
-

* Clock, Data and LE. Does not include f
INRF, fINIF and OSCIN.



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