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HM17CM256 bảng dữ liệu(PDF) 74 Page - Hynix Semiconductor

tên linh kiện HM17CM256
Giải thích chi tiết về linh kiện  128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
PDF  111 Pages
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nhà sản xuất  HYNIX [Hynix Semiconductor]
Trang chủ  http://www.skhynix.com/kor/main.do
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HM17CM256 bảng dữ liệu(HTML) 74 Page - Hynix Semiconductor

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HM17CM256
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BT command : inversion timing selection at line inversion display
BT=”0”: Negative tone display in specified area
BT=”1”: The image of specified area is blinked by every 32 frame.
Display example (BT=”1”)
And be cautious that LREV and BT commands have no influence on dummy segment driver circuit.
And the image selected by COMI0, COMI1 is excluded.
HYUNDAI
LCD DRIVER
Low Power and
Low Voltage
HYUNDAI
LCD DRIVER
Low Power and
Low Voltage
Line inversion display example (LREV=”1”,BT=”1”)
(34-30) Dummy segment driver address selection ( Refer to dummy segment drive related description. )
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
0
1
1
0
0
1
*
*
*
DMY
( reset :{DMY}=0H, read address :8H) * : “Don’t care”
When data is to be written to dummy segment driver, this register is active (DMY=”1”).
DMY=”0”: normal display RAM access
DMY=”1”: display data access to dummy segment driver
Normal segment drivers acquire display data from display RAM, but dummy segment drivers acquire
display data from corresponding register not from display RAM.
The capacity of register is 4 bytes.
That is correspond to SEGSA0~SEGSA3
SEGSB0~SEGSB3
SEGSC0~SEGSC3 output.
When accessing with DMY = “1”, address setting is valid by only X address.
There is 4 byte capacity,
and so 00H, 01H, 02H, 03H is valid at 8 bits mode and 00H, 01H is valid at 16 bits mode.
There is no
Changes per
every 32 frame.
line inversioin start address
line inversioin end address
Changes per
every 32 frame.



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