AT91SAM_14 datasheet(16/50 Pages) ATMEL

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SAM7S Series [DATASHEET]

6175KS–ATARM–25-Oct-12

Processor and Architecture

7.1

ARM7TDMI Processor

RISC processor based on ARMv4T Von Neumann architecture

Runs at up to 55 MHz, providing 0.9 MIPS/MHz

Two instruction sets

ARM® high-performance 32-bit instruction set

Thumb® high code density 16-bit instruction set

Three-stage pipeline architecture

Instruction Fetch (F)

Instruction Decode (D)

Execute (E)

7.2

Debug and Test Features

Integrated EmbeddedICE™ (embedded in-circuit emulator)

Two watchpoint units

Test access port accessible through a JTAG protocol

Debug communication channel

Debug Unit

Two-pin UART

Debug communication channel interrupt handling

Chip ID Register

IEEE1149.1 JTAG Boundary-scan on all digital pins

7.3

Memory Controller

Bus Arbiter

Handles requests from the ARM7TDMI and the Peripheral DMA Controller

Address decoder provides selection signals for

Three internal 1 Mbyte memory areas

One 256 Mbyte embedded peripheral area

Abort Status Registers

Source, Type and all parameters of the access leading to an abort are saved

Facilitates debug by detection of bad pointers

Misalignment Detector

Alignment checking of all data accesses

Abort generation in case of misalignment

Remap Command

Remaps the SRAM in place of the embedded non-volatile memory

Allows handling of dynamic exception vectors

Embedded Flash Controller

Embedded Flash interface, up to three programmable wait states

Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states

Key-protected program, erase and lock/unlock sequencer

Single command for erasing, programming and locking operations

Interrupt generation in case of forbidden operation

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