HTG12N0 datasheet(26/30 Pages) HOLTEK

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OR A,[R1R0]

Logical OR accumulator with data memory

Machine Code

0 0 0 1 1 1 0 0

Description

Data in the accumulator is logically OR with the data memory addressed

by the register pair “R1,R0”.

Operation

ACC

← ACC “OR” M(R1,R0)

OR [R1R0],A

Logical OR data memory with accumulator

Machine Code

0 0 0 1 1 1 1 1

Description

Data in the data memory addressed by the register pair “R1,R0” is logical

OR with the accumulator.

Operation

M(R1,R0)

← M(R1,R0) “OR” ACC

OUT Pi,A

Output accumulator data to port-i

Machine Code

0 0 1 1 0 0 0 0 PA

0 0 1 1 0 1 0 0 PC

Description

The data in the accumulator is transferred to the port-i and latched.

Operation

← ACC; Pi=PA or PC

READ MR0A

Read ROM code of current page to M(R1,R0) and ACC

Machine Code

0 1 0 0 1 1 1 0

Description

The 8-bits of ROM code (current page) addressed by ACC and R4 are

moved to the data memory M(R1,R0) and accumulator. The high nibble of

the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is

loaded to accumulator. The address of the ROM code are specified below :

Current page

→ ROM code address bit 12~8

ACC

→ ROM code address bit 7~4

→ ROM code address bit 3~0

Operation

M(R1R0)

← ROM code (high nibble)

ACC

← ROM code (low nibble)

READ R4A

Read ROM code of current page to R4 and accumulator

Machine Code

0 1 0 0 1 1 0 0

Description

The 8-bits of ROM code (current page) addressed by ACC and M(R1,R0)

are moved to the working register R4 and accumulator. The high nibble of

the ROM code is loaded to R4 and the low nibble of the ROM code is loaded

to the accumulator. The address of the ROM code are specified below:

Current page

→ ROM code address bit 12~8

ACC

→ ROM code address bit 7~4

M(R1,R0)

→ ROM code address bit 3~0

Operation

← ROM code (high nibble)

ACC

← ROM code (low nibble)

HTG12N0

18th Mar ’99

HTG12N0 bảng dữ liệu(PDF) 26 Page - Holtek Semiconductor Inc

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