HTG12B0 datasheet(13/33 Pages) HOLTEK

13 / 33 page

HTG12B0

September 8, 1999

LCD driver output

All of the LCD segments are random after an

initial clear. The bias voltage circuits of the

LCD display is built-in and no external resistor

is required.

The output number of the HTG12B0 LCD

driver is 40´16 which can directly drive an LCD

with 1/16 duty cycle and 1/4 bias.

The frequency of the LCD driving clock source

can be selected from RTC OSC or system clock

by accessing bit 1 of LCDC.

There are many frequency division of the LCD

clock which can be selected by mask option ei-

ther from RTC OSC or system clock.

· RTC OSC

Frequency of LCD clock = 16384

....where n=0~7

· System clock

Frequency of LCD clock = f64

SYS

....where n=0~5

LCD driver output can be enabled or disabled

by setting LCDC 3 without the influence of the

related memory condition.

LCD driver output is enabled by setting LCDC3

as ²1², and disabled by setting LCDC 3 as ²0².

Function

LCDC

Select LCD bank

0=Bank 0 (Com0~7)

1=Bank 1 (Com8~15)

Select LCD clock source

0=RTC OSC (32768Hz)

1=System clock

PM3 edge latch control bit

1=Enabled

0=Disabled

Control LCD display

0=OFF

1=ON

An example of an LCD driving waveform (1/16

duty and 1/4 bias) is shown below.

VLCD is fixed at 4.4V when VDD is from 2.4V to

3.6V.

LCDC Register

FE H

F C H

FA H

F8 H

B4 H

B 2 H

B0 H

B I T

CO M

DI SPL AY M E M O R Y

SEG M E N T

FF H

FDH

F B H

F9 H

B5 H

B 3 H

B1 H

LCD display memory (LCDC0=1)

VL C D

3/ 4V L C D

2/ 4V L C D

1/ 4V L C D

GN D

CO M 0

1024H z

64H z

CO M 1

SE G 0

VL C D

3/ 4V L C D

2/ 4V L C D

1/ 4V L C D

GN D

VL C D

3/ 4V L C D

2/ 4V L C D

1/ 4V L C D

GN D

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