HT8955 datasheet(4/7 Pages) HOLTEK

4 / 7 page

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VDD

Conditions

VIH

“H” Input Voltage

—

0.7VDD

—VDD

VOMAX

Maximum Output Voltage

RL>470k

Ω

11.5

—

Maximum Delay Time

SEL=open, 25kHz

sampling rate

0.15

0.2

—

SEL=VSS, 25kHz

sampling rate

0.6

0.8

—

S/N

Signal to Noise Ratio

VO=1V, 400Hz

BW=10kHz

—55

—

THD

Total Harmonic Distortion

VO=1V, 400Hz

BW=7kHz

—0.5

—

Functional Description

The HT8955A is a single chip LSI with an exter-

nal DRAM. It is designed for processing audio

signal delay. The chip includes a built-in pre-

amplifier, 10-bit A/D and D/A converters. The

A/D and D/A converters ensure low distortion as

well as high S/N ratio of the audio delay system.

The chip also provides two sets of oscillation

circuit for system sampling rate and audio echo

delay time.

Playing function block diagram

System oscillator

The HT8955A provides two oscillators, one for

the sampling rate and one for echo delay time.

The sampling rate oscillator requires an exter-

nal resistor between the OSC1 and OSC2 pins.

A higher sampling rate (25~50kHz) can thus be

derived by adjusting the oscillation resistor

without having a sophisticated low pass filter.

The delay time oscillator, on the other hand,

demands an external resistor between the

OSC3 and OSC4 pins. By altering the oscilla-

tion resistor, its delay time can be continuously

adjusted up to 0.8/0.2 seconds at a 25kHz sam-

pling rate for DRAM of 256Kb/64Kb.

DRAM selection

The HT8955A can interface with a DRAM for

storing delay signals. The type along with the

maximum delay time of DRAM is determined

by the status of the SEL pin as shown:

SEL Connection

DRAM

Type

Delay Time

VDD or Open

64Kb

0.2 seconds

VSS

256Kb

0.8 seconds

HT8955A

5th May ’98

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