HT6576 datasheet(5/14 Pages) HOLTEK

5 / 14 page

• BIT 4: ENABLE PARITY INTERRUPT

When set, this bit causes the IRQ signal to be asserted if a parity error is detected.

• BIT 3: ENABLE EOP INTERRUPT

When set, this bit causes the IRQ signal to be asserted if EOP is received from the DMA controller.

• BIT 2: MONITOR BUSY

When set, this bit causes the IRQ signa asserted when BSY changes to the inactive state for at

least a bus settle delay.

• BIT 1: DMA MODE

• BIT 0: Arbitrate

When set, this bit starts the arbitration process.

Address 3: Target command register

LAST BYTE

ASSERT

REQ

ASSERT

MSG

ASSERT

C/D

ASSERT

I/O

R/W

• BIT 7: LAST BYTE SEND (READ ONLY)

• BIT 3: ASSERT REQ

WHEN SET, THE REQ SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)

• BIT 2: ASSERT MSG

WHEN SET, THE MSG SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)

• BIT 1: ASSERT C/D

WHEN SET, THE C/D SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)

• BIT 0: ASSERT I/O

WHEN SET, THE I/O SIGNAL IS ASSERTED ON THE SCSI BUS (IN TAGRTE MODE)

Address 4: Current SCSI Bus Register

READ

RST

BSY

REQ

MSG

C/D

I/O

SEL

DBP

WRITE

–SELECT ENABLE REGISTER

SID7

SID6

SID5

SID4

SID3

SID2

SID1

SID0

HT6576A

14th July ’97

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