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HT48RA0A bảng dữ liệu(PDF) 3 Page - Holtek Semiconductor Inc |
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HT48RA0A bảng dữ liệu(HTML) 3 Page - Holtek Semiconductor Inc |
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3 / 31 page ![]() D.C. Characteristics Ta=25 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions VDD Operating Voltage ¾ LVR disabled 2.2 ¾ 3.6 V IDD Operating Current 3V No load, fSYS=4MHz ¾ 0.7 1.5 mA ISTB Standby Current 3V No load, system HALT ¾¾ 1 mA VIL1 Input Low Voltage for I/O Ports 3V ¾ 0 ¾ 0.3VDD V VIH1 Input High Voltage for I/O Ports 3V ¾ 0.7VDD ¾ VDD V VIL2 Input Low Voltage (RES)3V ¾ 0 ¾ 0.4VDD V VIH2 Input High Voltage (RES)3V ¾ 0.9VDD ¾ VDD V IOL I/O Ports Sink Current 3V VOL=0.1VDD 1.5 2.5 ¾ mA IOH PC0/REM Output Source Current 3V VOH=0.9VDD -1 -1.5 ¾ mA RPH1 Pull-high Resistance of PA Port, PB0~PB1 and RES 3V ¾¾ 60 ¾ k W RPH2 Pull-high Resistance of PB2~PB7 3V ¾¾ 60 ¾ k W A.C. Characteristics Ta=25 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions fSYS System Clock 3V ¾ 400 ¾ 4000 kHz tRES External Reset Low Pulse Width ¾¾ 1 ¾¾ ms tSST System Start-up Timer Period ¾ Power-up or wake-up from HALT ¾ 1024 ¾ tSYS Note: tSYS=1/fSYS HT48RA0A Rev. 1.70 3 July 16, 2003 Functional Description Execution Flow The HT48RA0A system clock can be derived from a crystal/ceramic resonator oscillator. It is internally di- vided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de- coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc- tion to effectively execute within one cycle. If an instruc- tion changes the program counter, two cycles are required to complete the instruction. T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 F e t c h I N S T ( P C ) E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 ) E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 ) E x e c u t e I N S T ( P C + 1 ) P C P C + 1 P C + 2 S y s t e m C l o c k I n s t r u c t i o n C y c l e P C Execution flow |
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