Z80C30 datasheet(39/83 Pages) ZILOG

39 / 83 page

PS011707-1013

Functional Descriptions

CMOS SCC Serial Communications Controller

Product Specification

The sequence for operation of the byte count and FIFO logic is to read the registers in the

following order. RR7, RR6, and RR1 (reading RR6 is optional). Additional logic prevents

the FIFO from being emptied by multiple reads from RR1. The read from RR7 latches the

FIFO empty/full status bit (D6) and steers the status multiplexer to read from the SCC

megacell instead of the status FIFO (since the status FIFO is empty). The read from RR1

Figure 13. SDLC Frame Status FIFO

Over

Equal

Reset on Flag Detect

Increment on Byte Detection

Enable Count in SDLC

End of Frame Signal

Status Read Comp

Tail Pointer

4-Bit Counter

Head Pointer

4-Bit Counter

4-Bit Comparator

14 Bits

Byte Counter

Frame Status FIFO Circuitry

5 Bits

FIFO Array

10 Deep by 19 Bits Wide

SCC Status Reg

Residue Bits (3)

Overrun, CRC Error

RR1

5 Bits

6 Bits

8 Bits

6-Bit MUX

2 Bits

EOF = 1

6 Bits

RR1

Bit 7 Bit 6

Bits 5-0

RR6

FIFO Enable

RR7 D5-D0 + RR6 D7-D0

Byte Counter Contains 14 bits

for a 16 KByte maximum count

RR7 D6

FIFO Data available status bit Status Bit set to 1

When reading from FIFO

RR7 D7

FIFO Overflow Status Bit

MSB pf RR(7) is set on Status FIFO overflow

WR(15) Bit 2

Set Enables

Status FIFO

In SDLC Mode the following definitions apply

Interface

to SCC

Z80C30 bảng dữ liệu(PDF) 39 Page - Zilog, Inc.

Z80C30 bảng dữ liệu(HTML) 39 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

bảng dữ liệu tải về

Link URL