WM8960 datasheet(52/92 Pages) WOLFSON

52 / 92 page

WM8960

Production Data

PD, August 2013, Rev 4.2

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised in

Table 33. MS selects audio interface operation in master or slave mode. In Master mode BCLK,

ADCLRC and DACLRC are outputs. The frequency of ADCLRC and DACLRC is set by the bits

ADCDIV and DACDIV and the frequency of BCLK is set by the bits BCLKDIV (See "Clocking and

Sample Rates"). In Slave mode BCLK, ADCLRC and DACLRC are inputs.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

Digital Audio

Interface

Format

ALRSWAP

Left/Right ADC channel swap

1 = Swap left and right ADC data in

audio interface

0 = Output left and right data as normal

BCLKINV

BCLK invert bit (for master and slave

modes)

0 = BCLK not inverted

1 = BCLK inverted

Master / Slave Mode Control

0 = Enable slave mode

1 = Enable master mode

DLRSWAP

Left/Right DAC Channel Swap

0 = Output left and right data as normal

1 = Swap left and right DAC data in

audio interface

LRP

Right, left and I

2S modes – LRCLK

polarity

0 = normal LRCLK polarity

1 = invert LRCLK polarity

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK rising

edge after LRC rising edge (mode A)

1 = MSB is available on 1st BCLK rising

edge after LRC rising edge (mode B)

3:2

WL[1:0]

Audio Data Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits (see Note)

1:0

FORMAT[1:0]

Audio Data Format Select

00 = Right justified

01 = Left justified

10 = I

2S Format

11 = DSP Mode

Table 33 Audio Data Format Control

Note: Right Justified mode does not support 32-bit data.

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