AS3709 datasheet(34/74 Pages) AMSCO

34 / 74 page

AS3709 – 34

ams Datasheet, Confidential: 2013-Aug [1-02]

Det a il e d De sc r i pt ion - S y s t em F u nc t i on s

Interrupt Generation

The interrupt controller generates an interrupt request for the

host controller as soon as one or more of the bits in the Interrupt

1…2 register are set by pulling low pin XINT (XINT has to be

selected as a GPIO output function). All the interrupt sources

can be enabled in the Interrupt Mask 1…2 register. The

Interrupt 1…2 registers are cleared automatically after the host

controller has read them. To prevent the AS3709 device from

losing an interrupt event, the register that is read is captured

before it is transmitted to the host controller via the serial

interface. As soon as the transmission of the captured value is

complete a logical AND operation with the bit wise inverted

captured value is applied to the register to clear all interrupt

bits that have already been transmitted. Clearing the read

interrupt bits takes 2 clock cycles, a read access to the same

value of ‘0’. Note that an interrupt that has been present at the

previous read access will be cleared as well in case it occurs

again before the clearing process has completed.

During a read access to one of the interrupt registers, the GPIO

pin (GPIO output function) will be released. As soon as the

transferred bits of the interrupt register have been cleared the

GPIO pin (GPIO output function) will be pulled low in case a new

interrupt has occurred in the meantime. By doing so, the

interrupt controller will work correctly with host controllers

that are edge- and level-sensitive on their interrupt request

input. Multiple byte read access is recommended to avoid

reading the Interrupt 1 register over and over again in response

to a new interrupt that has occurred in the same register (and

thus pulling low the GPIO pin) before the Interrupt 2 register

has been read.

2-Wire-Serial Control Interface

Feature List

• Fast-mode capability (max. SCL-frequency is 400 kHz)

• 7+1-bit addressing mode

• 60h x 8-bit data registers (word address 0x00 - 0x60)

• Write formats: Single-Byte-Write, Page-Write

• Read formats: Current-Address-Read, Random-Read,

Sequential-Read

• SDA input delay and SCL spike filtering by integrated

RC-components

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