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LMP92018 bảng dữ liệu(PDF) 8 Page - Texas Instruments

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tên linh kiện LMP92018
Giải thích chi tiết về linh kiện  LMP92018 Analog System Monitor and Controller
PDF  34 Pages
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LMP92018 bảng dữ liệu(HTML) 8 Page - Texas Instruments

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LMP92018
SNAS514B – NOVEMBER 2011 – REVISED MAY 2013
www.ti.com
Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, TA=25°C. Boldface limits are over
the temperature range of
−30°C ≤ TA ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output
CL = 200 pF unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INPUT CHARACTERISTICS (CSB, DIN, SCLK)
VIH
Input HIGH Voltage
0.7 x VIO
V
VIL
Input LO Voltage
0.3 x VIO
V
Hysteresis
250
mV
IIND
Digital Input Current
±0.005
±1
µA
CIND
Input Capacitance
4
pF
DIGITAL OUTPUT CHARACTERISTICS (GPIO[11:0])
IOUT = 200 µA
0.01
0.4
VOL
Output LO Voltage
V
IOUT = 1.6 mA
0.07
0.4
VGPIO = VDD = 5V
IOUT = 200µA
VGPIO-0.2
VOH
Output HI Voltage
V
IOUT = 1.6 mA
VGPIO-0.5
VGPIO = VDD = 5V
TRI-STATE Output Leakage
IOZH, IOZL
VGPIO=VDD
±5
µA
Current
COUT
Output Capacitance
4
pF
DIGITAL OUTPUT CHARACTERISTICS (DOUT)
IOUT = 200 µA
0.01
0.4
V
VOL
Output LO Voltage
IOUT = 1.6 mA
0.07
0.6
V
VIO = 3.3V
IOUT = 200 µA
VIO-0.2
VOH
Output HI Voltage
V
IOUT = 1.6 mA
VIO-0.5
VIO = 3.3V
TRI-STATE Output Leakage
IOZH, IOZL
VGPIO = 1.8V =VDD
±5
µA
Current
COUT
Output Capacitance
4
pF
DIGITAL OUTPUT CHARACTERISTICS (DRDYB)
IOUT = 1.6 mA
VOH_MAX
Maximum Output HI Voltage
VIO-0.5
µA
VIO = 3.3V to VDD
VOL
Output LO Voltage
Force 0V or VDD
0.01
V
POWER SUPPLY CHARACTERISTICS
VDD
Supply Voltage Range
4.75
5
5.5
VGPIO
GPIO Rail Range
1.8
VDD
V
VIO
SPI Rail Range
1.8
VDD
IDD
Supply Current, Conversion Mode
OUT[3:0] pins RL = ∞
4
mA
Power Consumption, Conversion
PWRCONV
OUT[3:0] pins RL = ∞
21
mW
Mode
Supply Current, Power-Down
IPD
50
µA
Mode
VPOR
Power-On Reset(6)
1.9
2.7
V
AC ELECTRICAL CHARACTERISTICS
tTRACK
ADC Track Time
Dictated by SPI bus activity
t8+9×t1
µs
tHOLD
ADC Hold Time
Dictated by SPI bus activity
15×t1
µs
25%FS to 75%FS code change,
ts
DAC Settling Time(7)
20
µs
RL = 2K, CL = 200 pF
(6)
During the power up the supply rail must ramp up beyond VPOR MIN for the device to acquire default state. After the supply rail has
reached the nominal level, the rail can drop as low as VPOR MAX for the current state to be maintained.
(7)
Device Specification is guaranteed by characterization and is not tested in production.
8
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP92018



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