ST1S32 datasheet(16/29 Pages) STMICROELECTRONICS

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Application information

ST1S32

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Doc ID 023246 Rev 1

Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage ripple in the order

of 1% of VINMAX.

The placement of the input capacitor is very important in order to avoid noise injection and

voltage spikes on the input voltage pin. So the CIN must be placed as close as possible to

the VIN_SW pin.

In Table 6 some multi-layer ceramic capacitors suitable for this device are reported.

A ceramic bypass capacitor, as close as possible to the VINA pin, so that additional parasitic

ESR and ESL are minimized, is suggested in order to prevent instability on the output

voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1µF.

5.2

Inductor selection

The inductance value fixes the current ripple flowing through the output capacitor. So the

minimum inductance value in order to have the expected current ripple must be selected.

The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current.

In continuous current mode (CCM), the inductance value can be calculated by the following

equation:

Equation 18

where TON is the conduction time of the high-side switch and TOFF is the conduction time of

the low-side switch (in CCM, FSW=1/(TON + TOFF)). The maximum current ripple, given the

VOUT, is obtained at maximum TOFF, that is at minimum duty cycle (see previous section to

calculate minimum duty). So by fixing

ΔIL=20% to 30% of the maximum output current, the

minimum inductance value can be calculated as:

Equation 19

where FSWMIN is the minimum switching frequency, according to Table 4.

Table 6.

Input MLCC capacitors

Manufacturer

Series

Cap value (µF)

Rated voltage (V)

Murata

GRM21

TDK

C3225

C3216

Taiyo Yuden

LMK212

ΔI

OUT

–

------------------------------

⋅

OUT

--------------

OFF

⋅

MIN

OUT

ΔI

MAX

----------------

MIN

–

SWMIN

-----------------------

⋅

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