MB40C328VPFV datasheet(12/16 Pages) FUJITSU

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MB40C328V

s TIMING DIAGRAM 4

Two-phase CLK input mode (CLKA, CLKB)

• CLK = “L” (DVSS) or “H” (DVDDI)

• CLKA = CLKB = 50 MHz (max)

• CKSEL = “L” (AVSS)

• DSEL = “L” (DVSS)

• RESET = “H” (DVDDI) or “L” (DVSS)

•CE = “L” (AVSS)

•OE = “L” (DVSS)

•VINA input — Sampling (A ch) at CLKA falling

Sampling (B ch) at CLKB falling

•DA0 to DA7 — Output (after 2.5 CLK + tpdD from Sampling) at CLKA rising

•DB0 to DB7 — Output (after 3 CLK + tpdD from Sampling) at CLKB rising

tpdD(max)

tpdD(typ)

tpdD(min)

tpdD(max)

tpdD(typ)

tpdD(min)

VIHD

VILD

VIHD

VILD

VOHD

VOLD

DA0 to DA7

VOHD

VOLD

DB0 to DB7

VOHD

VOLD

CLKOA

VOHD

VOLD

CLKOB

tWD−

tWD+

tAD

N(Ach)

+ 1(Bch)

− 6

− 7N − 5N − 3N − 1

+ 1

− 4N − 2

+ 2(Ach) N + 3(Bch) N + 4(Ach) N + 5(Bch) N + 6(Ach) N + 7(Bch)

tAD

tWD−

0.5 V

1.5 V

DVDD

−0.4 V

0.4 V

DVDD

− 0.4 V

0.4 V

tpdDO(max)

tpdDO(min)

0.4 V

tpdDO(typ)

DVDD

− 0.4 V

DVDD

− 0.5 V

DVDD

− 0.5 V

DA0 to DA7

CLKA input

CLKB input

VINA input

+ 2

ALL “L” fix

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