LM27341_14 datasheet(24/42 Pages) TI1

24 / 42 page

RTJA =

165

oC - 132oC

0.881 W

= 37.46

oC/W

LM27341, LM27342, LM27341Q, LM27342Q

SNVS497D – NOVEMBER 2008 – REVISED FEBRUARY 2010

www.ti.com

METHOD 3 EXAMPLE

The operating conditions are the same as the previous Efficiency Calculation:

VIN = 12V

VOUT = 3.3V

IOUT = 2A

fSW = 2 MHz

VD1 = 0.5V

RDCR = 20 mΩ

Internal Power Losses are:

PCOND = IOUT

2 x R

DSON x D

= 2

2 x 0.267Ω x .314

= 335 mW

(64)

PSW = (VIN x IOUT x fSW x tFALL)

= (12V x 2A x 2 MHz x 10nS)

= 480 mW

(65)

PQ = IQ x VIN

= 1.5 mA x 12V

= 29 mW

(66)

PBOOST = IBOOST x VBOOST

= 7 mA x 4.5V

= 37 mW

(67)

PINTERNAL = PCOND + PSW + PQ + PBOOST = 881 mW

(68)

Using a Texas Instruments MSOP-PowerPad evaluation board to determine the RθJA of the board. The four layer

PCB is constructed using FR4 with 2oz copper traces. There is a ground plane on the internal layer directly

beneath the device, and a ground plane on the bottom layer. The ground plane is accessed by fourteen 10 mil

vias. The board measures 2in x 2in (50.8mm x 50.8mm). It was placed in an oven with no forced airflow.

The ambient temperature was raised to 132 °C, and at that temperature, the device went into thermal shutdown.

RθJA can now be calculated.

(69)

To keep the Junction temperature below 125 °C for this layout, the ambient temperature must stay below 92 °C.

TA_MAX = TJ_MAX - (RθJA x PINTERNAL)

(70)

TA_MAX = 125 °C - (37.46 °C/W x 0.881 W)

(71)

TA_MAX = 92 °C

(72)

This calculation of the maximum ambient temperature is only 2.3 °C different from the calculation using method

2. The methods described above to find the junction temperature in the MSOP-PowerPad package can also be

used to calculate the junction temperature in the SON package. The 10-pin SON package has a RθJC = 9.1°C/W,

while RθJA can vary depending on the layout. RθJA can be calculated in the same manner as described in method

PCB Layout Considerations

COMPACT LAYOUT

The performance of any switching converter depends as much upon the layout of the PCB as the component

selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and

minimum generation of unwanted EMI.

Parasitic inductance can be reduced by keeping the power path components close together and keeping the

area of the loops small, on which high currents travel. Short, thick traces or copper pours (shapes) are best. In

particular, the switch node (where L1, D1, and the SW pin connect) should be just large enough to connect all

three components without excessive heating from the current it carries. The LM27341/LM27342 operates in two

distinct cycles (see Figure 32) whose high current paths are shown below in Figure 39:

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