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LM5113 bảng dữ liệu(PDF) 6 Page - Texas Instruments

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tên linh kiện LM5113
Giải thích chi tiết về linh kiện  5A, 100V Half-Bridge Gate Driver for Enhancement Mode GaN FETs
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LM5113 bảng dữ liệu(HTML) 6 Page - Texas Instruments

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LI
HI
tHPLH
tLPLH
tHPHL
tLPHL
LO
HO
LI
HI
tMOFF
tMON
LO
HO
LM5113
SNVS725E – JUNE 2011 – REVISED JANUARY 2012
www.ti.com
Switching Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values
represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise
specified, VDD = VHB = 5V, VSS = VHS = 0V, No Load on LOL and LOH or HOL and HOH
(1).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tLPHL
LO Turn-Off Propagation Delay
LI Falling to LOL Falling
26.5
45.0
ns
tLPLH
LO Turn-On Propagation Delay
LI Rising to LOH Rising
28.0
45.0
ns
tHPHL
HO Turn-Off Propagation Delay
HI Falling to HOL Falling
26.5
45.0
ns
tHPLH
HO Turn-On Propagation Delay
HI Rising to HOH Rising
28.0
45.0
ns
tMON
Delay Matching: LO on & HO off
1.5
8.0
ns
tMOFF
Delay Matching: LO off & HO on
1.5
8.0
ns
tHRC
HO Rise Time (0.5V - 4.5V)
CL = 1000 pF
7.0
ns
tLRC
LO Rise Time (0.5V – 4.5V)
CL = 1000 pF
7.0
ns
tHFC
HO Fall Time (0.5V - 4.5V)
CL = 1000 pF
1.5
ns
tLFC
LO Fall Time (0.5V - 4.5V)
CL = 1000 pF
1.5
ns
tPW
Minimum Input Pulse Width that Changes
10
ns
the Output
tBS
Bootstrap Diode Reverse Recovery Time
IF = 100mA,
40
ns
IR = 100mA
(1)
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Timing Diagram
Figure 3. Timing Diagram
6
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Product Folder Links: LM5113



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