ADC12D040

www.ti.com

SNAS171D – MAY 2004 – REVISED DECEMBER 2005

CLK

The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock

signal in the range of 100 kHz to 55 MHz with rise and fall times of less than 3ns. The trace carrying the clock

signal should be as short as possible and should not cross any other signal line, analog or digital, not even at

90°.

If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point

where the accuracy of the output data will degrade. This is what limits the lowest sample

The ADC clock line should be considered to be a transmission line and be series terminated at the source end to

match the source impedance with the characteristic impedance of the clock line. It generally is not necessary to

terminate the far (ADC) end of the clock line, but if a single clock source is driving more than one device (a

condition that is generally not recommended), far end termination may be needed. Far end termination is a series

RC with the resistor being the same as the characteristic impedance of the clock line. The capacitor should have

a minimum value of

The far end termination should be near but beyond the ADC clock pin as seen from the clock source.

The duty cycle of the clock signal can affect the performance of any A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC12040 is designed to maintain performance over a range of duty cycles. While it is

specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over a

clock duty cycle range of 40% to 60%.

Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application

Note AN-905 for information on setting characteristic impedance.

OEA, OEB

The OEA and OEB pin, when high, put the output pins of their respective converters into a high impedance state.

When either of these pins is low the corresponding outputs are in the active state. The ADC12D040 will continue

to convert whether these pins are high or low, but the output can not be read while the pin is high.

Since ADC noise increases with increased output capacitance at the digital output pins, do not use the TRI-

STATE outputs of the ADC12L066 to drive a bus. Rather, each output pin should be located close to and drive a

single digital input pin. To further reduce ADC noise, a 100

Ω resistor in series with each ADC digital output pin,

located close to their respective pins, should be added to the circuit.

The PD Pin

The PD pin, when high, holds the ADC12D040 in a power-down mode to conserve power when the converter is

not being used. The power consumption in this state is 75 mW with a 40 MHz clock and 40mW if the clock is

stopped when PD is high. The output data pins are undefined in the power down mode and the data in the

pipeline is corrupted while in the power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the capacitors on pins 4, 5, 6, 12, 13 and

14. These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry

before conversions can be accurate. Smaller capacitor values allow faster recovery from the power down mode,

but can result in a reduction in SNR, SINAD and ENOB performance.

The OF Pin

The output data format is offset binary when the OF pin is at a logic low or 2’s complement when the OF pin is at

a logic high. While the sense of this pin may be changed "on the fly," doing this is not recommended as the

output data could be erroneous for a few clock cycles after this change is made.

Copyright © 2004–2005, Texas Instruments Incorporated

Submit Documentation Feedback

21

Product Folder Links: ADC12D040