TAS5729MD datasheet(35/59 Pages) TI1

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TAS5729MD

www.ti.com

SLOS836A – MAY 2013 – REVISED JUNE 2013

CLOCK CONTROL REGISTER (0x00)

The clocks and data rates are automatically determined by the TAS5729MD. The clock control register contains

the autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.

Table 5. Clock Control Register (0x00)

FUNCTION

–

fS = 32-kHz sample rate

–

Reserved

–

Reserved

–

fS = 44.1/48-kHz sample rate

(1)

–

fS = 16-kHz sample rate

–

fS = 22.05/24-kHz sample rate

–

fS = 8-kHz sample rate

–

fS = 11.025/12-kHz sample rate

–

MCLK frequency = 64 × fS

(2)

–

MCLK frequency = 128 × fS

(2)

–

MCLK frequency = 192 × fS

(3)

–

MCLK frequency = 256 × fS

(1) (4)

–

MCLK frequency = 384 × fS

–

MCLK frequency = 512 × fS

–

Reserved

–

Reserved

–

Reserved(1)

–

Reserved(1)

(1)

Default values are in bold.

(2)

Only available for 44.1-kHz and 48-kHz rates

(3)

Rate only available for 32/44.1/48-KHz sample rates

(4)

Not available at 8 kHz

DEVICE ID REGISTER (0x01)

The device ID register contains the ID code for the firmware revision.

Table 6. General Status Register (0x01)

FUNCTION

Identification code(1)

(1)

Default values are in bold.

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