AT25DF081A datasheet(39/54 Pages) ETC2

39 / 54 page

8715C–SFLSH–1/2013

AT25DF081A

Figure 12-2. Read Manufacturer and Device ID

12.3 Deep Power-Down

During normal operation, the device will be placed in the standby mode to consume less power as long as the CS

pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability

to place the device into an even lower power consumption state called the Deep Power-Down mode.

When the device is in the Deep Power-Down mode, all commands including the Read Status Register command

will be ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be

ignored, the mode can be used as an extra protection mechanism against program and erase operations.

Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode of

B9h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored.

When the CS pin is deasserted, the device will enter the Deep Power-Down mode within the maximum time of

tEDPD.

The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on

an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the

standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode after a power-

cycle.

The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase

cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation

has been completed in order for the device to enter the Deep Power-Down mode.

OPCODE

MANUFACTURED ID

DEVICE ID

BYTE 1

DEVICE ID

BYTE 2

EDI

STRING LENGTH

EDI

DATA BYTE 1

Note: Each transition

shown for SI and SO represents one byte (8 bits)

AT25DF081A bảng dữ liệu(PDF) 39 Page - List of Unclassifed Manufacturers