3D6701 datasheet(2/4 Pages) DATADELAY

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3D6701

Doc #14015

DATA DELAY DEVICES, INC.

6/9/2014

Tel: 973-773-2299

Fax: 973-773-9672

http://www.datadelay.com

THEORY OF OPERATION

The 3D6701 clock synchronizer architecture is

shown in Figure 2. The FIN input is assumed to

come from a stable clock source, such as a

crystal oscillator. A rising edge on the GIN input

initiates the phase detection process. Once the

phase of the clock with respect to the gate has

been resolved, a delay line is adjusted to match

the phases of the two signals.

There is a finite resolution to the phase detection

process (typically under 500ps), so that, from one

gate trigger to the next, there will remain some

residual gate-to-output jitter. However, for a given

gate, the jitter from one clock cycle to the next is

equal to the jitter of the reference clock itself.

The 3D6701 also contains a programmable

divider that reduces the output frequency by an

amount given by the D7:0 inputs. FOUT is given by

FIN / (D+1), so that the output frequency may

range from FIN (D=0) to FIN / 256 (D=255). When

GIN returns low, the output returns to a low level

and remains there until the next rising edge of

GIN.

The performance of CMOS integrated circuits is

strongly dependent on power supply stability. It is

essential that the power supply pins be

adequately bypassed and filtered. In addition, the

power bus should be of as low an impedance

construction as possible. Power planes are

preferred.

When operating at 3.3V, tie the SEL input to

GND. When operating at 5.0V, tie the SEL

input to VDD.

DEVICE SPECIFICATIONS

TABLE 1: ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

DC Supply Voltage

VDD

-0.3

7.0

Input Pin Voltage

VIN

-0.3

VDD+0.3

Input Pin Current

IIN

-1.0

1.0

25C

Storage Temperature

TSTRG

-55

150

Lead Temperature

TLEAD

300

10 sec

Phase

Resolver

Programmable

Delay Line

8-Bit

Divider

FOUT

GIN

FIN

D7:0

Figure 2: 3D6701 Functional Block Diagram

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