19

* This specification are subject to be changed without notice.

EM73201

4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT

Preliminary

7.20.1999

0123

system reset

WDT control

WDT counter

WDT

command port

RESET pin

R

S

Q

F/F

counter clear request

P21

fc/2

17

P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to reset pin, user can

use this time up signal (active low) to reset CPU and initialize system.

Program example:

LDIA #0001B;

OUTA P21

; set WDT detection time and clear WDT counter

::

RESETTING FUNCTION

When CPU in normal working condition and RESET pin holds in low level for three instruction cycles

at least, then CPU begins to initialize the whole internal states, and when RESET pin changes to high

level, CPU begins to work in normal condition.

The CPU internal state during reset condition is as following table :

Hardware condition in RESET state

Initial value

Program counter

000h

Status flag

01h

Interrupt enable flip-flop ( EI )

00h

MASK0 ,1, 2, 3

00h

Interrupt latch(IL)

00h

P4, P5, P16, P25, P28

00h

P1, P7, P8

0Fh

XIN

Start oscillation

P21

3

2

1

0

initial value :0000

CWC

Clear watch-dog-timer counter

Clear counter then return to 1

Nothing

0

1

CWC

*

*

WDT

WDT

Set watch-dog-timer

detect time

0

1

System clock frequency

4MHz

32KHz

98ms

229ms

12sec

28sec