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EL4093CS bảng dữ liệu(PDF) 13 Page - Elantec Semiconductor |
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EL4093CS bảng dữ liệu(HTML) 13 Page - Elantec Semiconductor |
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13 / 16 page  EL4093C 300 MHz DC-Restored Video Amplifier Applications Information Contd Choice of Hold Capacitor The EL4093 has been designed to work with a hold capacitor of 22 nF With this value of CHOLD the droop rate and hold step are negligi- bly small for most applications In addition with the special boost circuits inside the SH fast ac- quisition is possible even using a hold capacitor of this size Figure 5 below shows the input and output of the DC-restored amplifier while the SH is in sample mode Applying a a1V step to the non-inverting input of the CFA the output of the CFA jumps to a2V The SH however then tries to autozero the system by driving the CFA output back to the reference voltage Since the input differential across the SH is initially a 2V the boost circuits turn on and supply 85 mA of charge current to the hold capacitor The boost circuit remains on until the CFA out- put has come to within 50 mV of the reference Note that this event took only 320 ns settling to within 1% of the final value takes another 2 ms Thus for a 1V input step acquisition takes only one to two NTSC scan lines 4093 – 41 Figure 5 Autozero Mechanism Restores Amplifier Output to Ground after a1V Step at Input A natural question arises as to whether there are other CHOLD values that can be used In one di- rection increasing CHOLD will further reduce the droop and hold step but lengthen the acquisition time Since the droop and hold step are already small to begin with there is no apparent advan- tage to increasing CHOLD In the other direction decreasing CHOLD would increase the droop and hold step but shorten the acquisition time There is however a caveat to reducing CHOLD too small a CHOLD would cause the autozero loop to oscillate The reason is that when the SH boost circuit turns on the input stage gm increases drastically and the cir- cuit becomes nonlinear A sufficiently large CHOLD must be used to suppress the non-lineari- ty and force the loop to settle For example it has been found that a CHOLD of 470 pF results in 1VP-P oscillation around 10 MHz at the CFA output The minimum recommended value for CHOLD is 22 nF With this value the loop remains stable over the entire operating temperature range (b40 Cto a85 C) The greatest instability oc- curs at low temperatures where we observe from the performance curves that the SH gm’s and hence the GBWP are at their maximum If the operating range is restricted to room temperature or above then 15 nF is sufficient to keep the loop stable At this value of CHOLD the acquisi- tion time reduces to about 15 ms Video Performance and Application Although the EL4093 is intended for high speed video applications such as SVGA it also offers excellent performance for NTSC with 004% dG and 002 dP at 358 MHz Some application con- siderations however are required for handling NTSC signals Referring back to Figure 2 recall that typically the autozero interval lies in the back porch por- tion of video containing the colorburst pulse When the SH compares the video to the refer- ence voltage during this period the colorburst (40 IREP-P) triggers the SH boost circuit and prevents the autozero loop from settling 13 |
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