EP1C3 datasheet(39/385 Pages) ETC2

39 / 385 page

Altera Corporation

2–19

May 2008

Preliminary

Embedded Memory

In addition to true dual-port memory, the M4K memory blocks support

simple dual-port and single-port RAM. Simple dual-port memory

supports a simultaneous read and write. Single-port memory supports

non-simultaneous reads and writes. Figure 2–13 shows these different

M4K RAM memory port configurations.

Figure 2–13. Simple Dual-Port and Single-Port Memory Configurations

Note to Figure 2–13:

(1)

Two single-port memory blocks can be implemented in a single M4K block as long

as each of the two independent block sizes is equal to or less than half of the M4K

block size.

The memory blocks also enable mixed-width data ports for reading and

writing to the RAM ports in dual-port RAM configuration. For example,

the memory block can be written in ×1 mode at port A and read out in ×16

mode from port B.

The Cyclone memory architecture can implement fully synchronous

RAM by registering both the input and output signals to the M4K RAM

block. All M4K memory block inputs are registered, providing

synchronous write cycles. In synchronous operation, the memory block

generates its own self-timed strobe write enable (

wren) signal derived

from a global clock. In contrast, a circuit using asynchronous RAM must

generate the RAM

wren signal while ensuring its data and address

signals meet setup and hold time specifications relative to the

wren

data[]

wraddress[]

wren

inclock

inclocken

inaclr

rdaddress[]

rden

q[]

outclock

outclocken

outaclr

data[]

address[]

wren

inclock

inclocken

inaclr

q[]

outclock

outclocken

outaclr

Single-Port Memory (1)

Simple Dual-Port Memory

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